Clean up some inconsistencies with Request flags.

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 8cce5c1521fa9e5d6d1a7e50f0c0eda214740ef5..febc6d08126de8f6ab002d84561c5e2344099180 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -147,7 +147,7 @@ TLB::checkCacheability(RequestPtr &req)
   // or by the TLB entry
   if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
     // mark request as uncacheable
-    req->setFlags(req->getFlags() | Request::UNCACHEABLE);
+    req->setFlags(Request::UNCACHEABLE);
   }
   return NoFault;
 }

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 1b84a0784489e394dc85e2f03169e8038bcd6688..41b0f2043d8e2496ca63a36b4dc629ffef928820 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -837,7 +837,7 @@ handleSparcErrorRegAccess:
 regAccessOk:
 handleMmuRegAccess:
     DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
-    req->setMmapedIpr(true);
+    req->setFlags(Request::MMAPED_IPR);
     req->setPaddr(req->getVaddr());
     return NoFault;
 };

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 418f6ffb29c854715670144035eed70c5bda5d77..5280b9ba860a70da35fb99a06fddaa18eada4f01 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -197,7 +197,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
         panic("CPUID memory space not yet implemented!\n");
     } else if (prefix == IntAddrPrefixMSR) {
         vaddr = vaddr >> 3;
-        req->setMmapedIpr(true);
+        req->setFlags(Request::MMAPED_IPR);
         Addr regNum = 0;
         switch (vaddr & ~IntAddrPrefixMask) {
           case 0x10:
@@ -526,7 +526,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
         // space.
         assert(!(IOPort & ~0xFFFF));
         if (IOPort == 0xCF8 && req->getSize() == 4) {
-            req->setMmapedIpr(true);
+            req->setFlags(Request::MMAPED_IPR);
             req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
         } else if ((IOPort & ~mask(2)) == 0xCFC) {
             Addr configAddress =

diff --git a/src/mem/request.hh b/src/mem/request.hh
index 8ca6a59a72e1f08b229ab7fdbcedefc689b06633..c8c31ffcda6a3ed96d422f46987e09d948a86364 100644 (file)
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -347,6 +347,10 @@ class Request : public FastAlloc
         return _flags;
     }
 
+    /** Note that unlike other accessors, this function sets *specific
+       flags* (ORs them in); it does not assign its argument to the
+       _flags field.  Thus this method should rightly be called
+       setFlags() and not just flags(). */
     void
     setFlags(Flags flags)
     {
@@ -378,21 +382,6 @@ class Request : public FastAlloc
         return _flags & ASI_BITS;
     }
 
-    /** Accessor function for MMAPED_IPR flag. */
-    bool
-    isMmapedIpr()
-    {
-        assert(privateFlags.isSet(VALID_PADDR));
-        return _flags.isSet(MMAPED_IPR);
-    }
-
-    void
-    setMmapedIpr(bool r)
-    {
-        assert(VALID_VADDR);
-        _flags.set(MMAPED_IPR);
-    }
-
     /** Accessor function to check if sc result is valid. */
     bool
     extraDataValid()
@@ -452,7 +441,8 @@ class Request : public FastAlloc
         return _pc;
     }
 
-    /** Accessor Function to Check Cacheability. */
+    /** Accessor functions for flags.  Note that these are for testing
+       only; setting flags should be done via setFlags(). */
     bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
     bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
     bool isPrefetch() const { return _flags.isSet(PREFETCH); }
@@ -460,6 +450,7 @@ class Request : public FastAlloc
     bool isLocked() const { return _flags.isSet(LOCKED); }
     bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
     bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
+    bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
 
     bool
     isMisaligned() const