rename svremap to svshape

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 97e6aff2efcf0c2ca60af9300929bdcedf28e597..7a7d255bcec0ed5db19849c954d3ce1037ba2c98 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -38,11 +38,11 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
-# svremap
+# svshape
 
 SVM-Form
 
-* svremap SVxd, SVyd, SVzd, SVRM
+* svshape SVxd, SVyd, SVzd, SVRM
 
 Pseudo-code:
 

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 2cd1c30ed9c41b574ad66d44385c61c3fd865488..c598c4f6426f0a23355a477b175f033c06471df3 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1087,10 +1087,10 @@ class ISACaller:
             illegal = False
             name = 'setvl'
 
-        # and svremap not being supported by binutils (.long)
-        if asmop.startswith('svremap'):
+        # and svshape not being supported by binutils (.long)
+        if asmop.startswith('svshape'):
             illegal = False
-            name = 'svremap'
+            name = 'svshape'
 
         # sigh also deal with ffmadds not being supported by binutils (.long)
         if asmop == 'ffmadds':
@@ -1488,7 +1488,7 @@ class ISACaller:
             # to be able to know if it should apply in the next instruction.
             # also (if going to use this instruction) should disable ability
             # to interrupt in between. sigh.
-            self.last_op_svshape = asmop == 'svremap'
+            self.last_op_svshape = asmop == 'svshape'
 
         self.update_pc_next()
 

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 21d95c8d932ceededa77631d7cdb96ddc3446bf2..605a8b3da2693f9a3c8b03aa5670bc0272902ecb 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -95,6 +95,10 @@ def transform_radix2_complex(vec_r, vec_i, cos_r, sin_i):
                 # triple-nested for-loops
                 jl, jh = j, j+halfsize
 
+                print ("xform jl jh k", jl, jh, k,
+                        "vr h l", vec_r[jh], vec_r[jl],
+                        "vi h l", vec_i[jh], vec_i[jl])
+                print ("    cr k", cos_r[k], "si k", sin_i[k])
                 tpre =  vec_r[jh] * cos_r[k] + vec_i[jh] * sin_i[k]
                 tpim = -vec_r[jh] * sin_i[k] + vec_i[jh] * cos_r[k]
                 vec_r[jh] = vec_r[jl] - tpre
@@ -102,9 +106,9 @@ def transform_radix2_complex(vec_r, vec_i, cos_r, sin_i):
                 vec_r[jl] += tpre
                 vec_i[jl] += tpim
 
-                print ("xform jl jh k", jl, jh, k,
-                        "vr h l", vec_r[jh], vec_r[jl],
-                        "vi h l", vec_i[jh], vec_i[jl])
+                print ("    xform jl jh k", jl, jh, k,
+                        "\n       vr h l", vec_r[jh], vec_r[jl],
+                        "\n       vi h l", vec_i[jh], vec_i[jl])
                 k += tablestep
         size *= 2
 
@@ -118,7 +122,7 @@ class FFTTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_remap_fpmadds_fft(self):
-        """>>> lst = ["svremap 8, 1, 1, 1",
+        """>>> lst = ["svshape 8, 1, 1, 1",
                       "sv.ffmadds 2.v, 2.v, 2.v, 10.v"
                      ]
             runs a full in-place O(N log2 N) butterfly schedule for
@@ -133,7 +137,7 @@ class FFTTestCase(FHDLTestCase):
             SVP64 "REMAP" in Butterfly Mode is applied to a twin +/- FMAC
             (3 inputs, 2 outputs)
         """
-        lst = SVP64Asm( ["svremap 8, 1, 1, 1",
+        lst = SVP64Asm( ["svshape 8, 1, 1, 1",
                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v"
                         ])
         lst = list(lst)
@@ -198,7 +202,7 @@ class FFTTestCase(FHDLTestCase):
 
     def test_sv_remap_fpmadds_fft_svstep(self):
         """>>> lst = SVP64Asm( ["setvl 0, 0, 11, 1, 1, 1",
-                            "svremap 8, 1, 1, 1",
+                            "svshape 8, 1, 1, 1",
                             "sv.ffmadds 0.v, 0.v, 0.v, 8.v",
                             "setvl. 0, 0, 0, 1, 0, 0",
                             "bc 4, 2, -16"
@@ -212,7 +216,7 @@ class FFTTestCase(FHDLTestCase):
             (3 inputs, 2 outputs)
         """
         lst = SVP64Asm( ["setvl 0, 0, 11, 1, 1, 1",
-                        "svremap 8, 1, 1, 1",
+                        "svshape 8, 1, 1, 1",
                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v",
                         "setvl. 0, 0, 0, 1, 0, 0",
                         "bc 4, 2, -16"
@@ -409,23 +413,23 @@ class FFTTestCase(FHDLTestCase):
         """
         lst = SVP64Asm( ["setvl 0, 0, 11, 1, 1, 1",
                         # tpre
-                        "svremap 8, 1, 1, 1",
-                        "sv.fmuls 32, 0.v, 16.v",
-                        "svremap 8, 1, 1, 1",
-                        "sv.fmuls 33, 8.v, 20.v",
-                        "fadds 32, 32, 33",
+                        "svshape 8, 1, 1, 1",
+                        "sv.fmuls 24, 0.v, 16.v",
+                        "svshape 8, 1, 1, 1",
+                        "sv.fmuls 25, 8.v, 20.v",
+                        "fadds 24, 24, 25",
                         # tpim
-                        "svremap 8, 1, 1, 1",
-                        "sv.fmuls 34, 0.v, 20.v",
-                        "svremap 8, 1, 1, 1",
-                        "sv.fmuls 35, 8.v, 16.v",
-                        "fsubs 34, 34, 35",
+                        "svshape 8, 1, 1, 1",
+                        "sv.fmuls 26, 0.v, 20.v",
+                        "svshape 8, 1, 1, 1",
+                        "sv.fmuls 26, 8.v, 16.v",
+                        "fsubs 26, 26, 27",
                         # vec_r jh/jl
-                        "svremap 8, 1, 1, 1",
-                        "sv.ffadds 0.v, 0.v, 32",
+                        "svshape 8, 1, 1, 1",
+                        "sv.ffadds 0.v, 24, 25",
                         # vec_i jh/jl
-                        "svremap 8, 1, 1, 1",
-                        "sv.ffadds 8.v, 8.v, 34",
+                        "svshape 8, 1, 1, 1",
+                        "sv.ffadds 8.v, 26, 27",
 
                         # svstep loop
                         "setvl. 0, 0, 0, 1, 0, 0",
@@ -486,11 +490,11 @@ class FFTTestCase(FHDLTestCase):
             # complex numbers
             res_r, res_i = transform_radix2_complex(ar, ai, coer, coei)
 
-            for i, expected_r, expected_i in enumerate(zip(res_r, res_i)):
-                print ("i", i, float(sim.fpr(i)),
+            for i, (expected_r, expected_i) in enumerate(zip(res_r, res_i)):
+                print ("i", i, float(sim.fpr(i)), float(sim.fpr(i+8)),
                        "expected_r", expected_r,
                        "expected_i", expected_i)
-            for i, expected_r, expected_i in enumerate(zip(res_r, res_i)):
+            for i, (expected_r, expected_i) in enumerate(zip(res_r, res_i)):
                 # convert to Power single
                 expected_r = DOUBLE2SINGLE(fp64toselectable(expected_r ))
                 expected_r = float(expected_r)

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index 39768bf17068dd12958655eb95cb6ffd2324d548..0821769bbb4daf29bb99e56ef300f862e32c7e79 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -27,12 +27,12 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_remap1(self):
-        """>>> lst = ["svremap 2, 2, 3, 0",
+        """>>> lst = ["svshape 2, 2, 3, 0",
                        "sv.fmadds 0.v, 8.v, 16.v, 0.v"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
-        lst = SVP64Asm(["svremap 2, 2, 3, 0",
+        lst = SVP64Asm(["svshape 2, 2, 3, 0",
                        "sv.fmadds 0.v, 16.v, 32.v, 0.v"
                         ])
         lst = list(lst)
@@ -98,12 +98,12 @@ class DecoderTestCase(FHDLTestCase):
             #    self.assertEqual(sim.fpr(i+6), u)
 
     def test_sv_remap2(self):
-        """>>> lst = ["svremap 5, 4, 3, 0",
+        """>>> lst = ["svshape 5, 4, 3, 0",
                        "sv.fmadds 0.v, 8.v, 16.v, 0.v"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
-        lst = SVP64Asm(["svremap 4, 3, 3, 0",
+        lst = SVP64Asm(["svshape 4, 3, 3, 0",
                        "sv.fmadds 0.v, 16.v, 32.v, 0.v"
                         ])
         lst = list(lst)

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 48e437ba88d0fce30d2c4365eeeddb09ae48b5a5..b9099dc29b206660f1210da8c3b91942d2ab023f 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -279,6 +279,7 @@ _insns = [
     "setb",
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
+    "svshape",  # https://libre-soc.org/openpower/sv/remap
     "sim_cfg",
     "slbia", "sld", "slw", "srad", "sradi",
     "sraw", "srawi", "srd", "srw",

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 6fc57705d9ac6061c27fef69a45971a38b071214..c080ee026bc0e119f29e30db2d67b16c1706a820 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -197,8 +197,8 @@ class SVP64Asm:
             yield ".long 0x%x" % insn
             return
 
-        # and svremap.  note that the dimension fields one subtracted from each
-        if opcode == 'svremap':
+        # and svshape.  note that the dimension fields one subtracted from each
+        if opcode == 'svshape':
             insn = 22 << (31-5)          # opcode 22, bits 0-5
             fields = list(map(int, fields))
             insn |= (fields[0]-1) << (31-10) # SVxd       , bits 6-10
@@ -207,7 +207,7 @@ class SVP64Asm:
             insn |= (fields[3])   << (31-25) # SVRM       , bits 21-25
             insn |= 0b00001   << (31-30) # XO       , bits 26..30
             #insn &= ((1<<32)-1)
-            log ("svremap", bin(insn))
+            log ("svshape", bin(insn))
             yield ".long 0x%x" % insn
             return
 
@@ -916,7 +916,7 @@ def asm_process():
         ls = line.split("#")
         # identify macros
         op = ls[0].strip()
-        if op.startswith("setvl") or op.startswith("svremap"):
+        if op.startswith("setvl") or op.startswith("svshape"):
             ws, line = get_ws(ls[0])
             lst = list(isa.translate_one(ls[0].strip(), macros))
             lst = '; '.join(lst)
@@ -982,7 +982,7 @@ if __name__ == '__main__':
     ]
     lst = [
              'sv.fmadds 0.v, 8.v, 16.v, 4.v',
-             'svremap 8, 1, 1, 1',
+             'svshape 8, 1, 1, 1',
              'sv.ffadds 0.v, 8.v, 4.v',
             ]
     isa = SVP64Asm(lst, macros=macros)