+2015-10-12 Yao Qi <yao.qi@linaro.org>
+
+ * arch/aarch64-insn.c (emit_load_store): Rename to ...
+ (aarch64_emit_load_store): ... it. All callers updated.
+
2015-10-12 Yao Qi <yao.qi@linaro.org>
* arch/aarch64-insn.c (emit_insn): Rename to ...
/* Helper function emitting a load or store instruction. */
int
-emit_load_store (uint32_t *buf, uint32_t size,
- enum aarch64_opcodes opcode,
- struct aarch64_register rt,
- struct aarch64_register rn,
- struct aarch64_memory_operand operand)
+aarch64_emit_load_store (uint32_t *buf, uint32_t size,
+ enum aarch64_opcodes opcode,
+ struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand)
{
uint32_t op;
0 .. 32760 range (12 bits << 3). */
#define emit_ldr(buf, rt, rn, operand) \
- emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand)
+ aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand)
/* Write a LDRSW instruction into *BUF. The register size is 64-bit.
0 .. 16380 range (12 bits << 2). */
#define emit_ldrsw(buf, rt, rn, operand) \
- emit_load_store (buf, 3, LDRSW, rt, rn, operand)
+ aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand)
/* Write a TBZ or TBNZ instruction into *BUF.
int aarch64_emit_insn (uint32_t *buf, uint32_t insn);
-int emit_load_store (uint32_t *buf, uint32_t size,
- enum aarch64_opcodes opcode,
- struct aarch64_register rt,
- struct aarch64_register rn,
- struct aarch64_memory_operand operand);
+int aarch64_emit_load_store (uint32_t *buf, uint32_t size,
+ enum aarch64_opcodes opcode,
+ struct aarch64_register rt,
+ struct aarch64_register rn,
+ struct aarch64_memory_operand operand);
#endif
+2015-10-12 Yao Qi <yao.qi@linaro.org>
+
+ * linux-aarch64-low.c: Update all callers as emit_load_store
+ is renamed to aarch64_emit_load_store.
+
2015-10-12 Yao Qi <yao.qi@linaro.org>
* linux-aarch64-low.c: Update all callers of function renaming
struct aarch64_register rn,
struct aarch64_memory_operand operand)
{
- return emit_load_store (buf, 1, LDR, rt, rn, operand);
+ return aarch64_emit_load_store (buf, 1, LDR, rt, rn, operand);
}
/* Write a LDRB instruction into *BUF.
struct aarch64_register rn,
struct aarch64_memory_operand operand)
{
- return emit_load_store (buf, 0, LDR, rt, rn, operand);
+ return aarch64_emit_load_store (buf, 0, LDR, rt, rn, operand);
}
struct aarch64_register rn,
struct aarch64_memory_operand operand)
{
- return emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand);
+ return aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, STR, rt, rn, operand);
}
/* Helper function emitting an exclusive load or store instruction. */