cpu/vexriscv: update submodule

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 4b5a515d4bbb22df0eb44a6e53cc76b3da1ff470..cfbd3e0871e1f85336c6a7adbc75f3702b365e1d 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 4b5a515d4bbb22df0eb44a6e53cc76b3da1ff470
+Subproject commit cfbd3e0871e1f85336c6a7adbc75f3702b365e1d