must not add bus width parameter

diff --git a/ls180soc.py b/ls180soc.py
index 8d2789fbec71bf24bf359290e4c0e0c1014f3ed8..44a4ce8c1c20ac0e650325a3db0201dbca7374dd 100755 (executable)
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -362,7 +362,7 @@ class LibreSoCSim(SoCCore):
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
-            bus_data_width           = 64,
+            #bus_data_width           = 64, # don't add this! stops conversion
             csr_address_width        = 14, # limit to 0x8000
             cpu_variant              = variant,
             csr_data_width            = 8,