}
if (inst_module) {
+ bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
auto it = cell->attributes.find("\\abc9_box_seq");
if (it != cell->attributes.end()) {
int abc9_box_seq = it->second.as_int();
box_list.resize(abc9_box_seq+1);
box_list[abc9_box_seq] = cell;
// Only flop boxes may have arrival times
- if (!inst_module->get_bool_attribute("\\abc9_flop"))
+ if (!abc9_flop)
continue;
}
for (auto bit : sigmap(conn.second))
arrival_times[bit] = arrival;
}
+
+ if (abc9_flop)
+ continue;
}
}
// For flops only, create an extra 1-bit input that drives a new wire
// called "<cell>.abc9_ff.Q" that is used below
if (box_module->get_bool_attribute("\\abc9_flop"))
- box_inputs++;
+ box_inputs++;
std::get<0>(v) = box_inputs;
std::get<1>(v) = box_outputs;