Lower fddx and fddy and set the right bits in codegen.
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
case ppir_op_min:
f->op = ppir_codegen_vec4_acc_op_min;
break;
+ case ppir_op_ddx:
+ f->op = ppir_codegen_vec4_acc_op_dFdx;
+ break;
+ case ppir_op_ddy:
+ f->op = ppir_codegen_vec4_acc_op_dFdy;
+ break;
default:
break;
}
case ppir_op_select:
f->op = ppir_codegen_float_acc_op_sel;
break;
+ case ppir_op_ddx:
+ f->op = ppir_codegen_float_acc_op_dFdx;
+ break;
+ case ppir_op_ddy:
+ f->op = ppir_codegen_float_acc_op_dFdy;
+ break;
default:
break;
}
if (instr->slots[PPIR_INSTR_SLOT_TEXLD])
ctrl->sync = true;
+ if (instr->slots[PPIR_INSTR_SLOT_ALU_VEC_ADD]) {
+ ppir_node *node = instr->slots[PPIR_INSTR_SLOT_ALU_VEC_ADD];
+ if (node->op == ppir_op_ddx || node->op == ppir_op_ddy)
+ ctrl->sync = true;
+ }
+
+ if (instr->slots[PPIR_INSTR_SLOT_ALU_SCL_ADD]) {
+ ppir_node *node = instr->slots[PPIR_INSTR_SLOT_ALU_SCL_ADD];
+ if (node->op == ppir_op_ddx || node->op == ppir_op_ddy)
+ ctrl->sync = true;
+ }
+
for (int i = 0; i < 2; i++) {
if (instr->constant[i].num) {
uint16_t output[4] = {0};
return true;
}
+static bool ppir_lower_ddxy(ppir_block *block, ppir_node *node)
+{
+ assert(node->type == ppir_node_type_alu);
+ ppir_alu_node *alu = ppir_node_to_alu(node);
+
+ alu->src[1] = alu->src[0];
+ if (node->op == ppir_op_ddx)
+ alu->src[1].negate = !alu->src[1].negate;
+ else if (node->op == ppir_op_ddy)
+ alu->src[0].negate = !alu->src[0].negate;
+ else
+ assert(0);
+
+ alu->num_src = 2;
+
+ return true;
+}
+
static bool ppir_lower_texture(ppir_block *block, ppir_node *node)
{
ppir_load_texture_node *load_tex = ppir_node_to_load_texture(node);
[ppir_op_abs] = ppir_lower_abs,
[ppir_op_neg] = ppir_lower_neg,
[ppir_op_const] = ppir_lower_const,
+ [ppir_op_ddx] = ppir_lower_ddxy,
+ [ppir_op_ddy] = ppir_lower_ddxy,
[ppir_op_lt] = ppir_lower_swap_args,
[ppir_op_le] = ppir_lower_swap_args,
[ppir_op_load_texture] = ppir_lower_texture,
[nir_op_inot] = ppir_op_not,
[nir_op_ftrunc] = ppir_op_trunc,
[nir_op_fsat] = ppir_op_sat,
+ [nir_op_fddx] = ppir_op_ddx,
+ [nir_op_fddy] = ppir_op_ddy,
};
static ppir_node *ppir_emit_alu(ppir_block *block, nir_instr *ni)
PPIR_INSTR_SLOT_END
},
},
+ [ppir_op_ddx] = {
+ .name = "ddx",
+ .slots = (int []) {
+ PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
+ PPIR_INSTR_SLOT_END
+ },
+ },
+ [ppir_op_ddy] = {
+ .name = "ddy",
+ .slots = (int []) {
+ PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
+ PPIR_INSTR_SLOT_END
+ },
+ },
[ppir_op_and] = {
.name = "and",
.slots = (int []) {