Updated abc

diff --git a/Makefile b/Makefile
index 9a8bd9407195d31ad21a9ed44eb506e1b846d18b..f4f4678501ca227a0fe31905c8450687e6ecd4b3 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -27,7 +27,7 @@ YOSYS_VER := 0.0.x
 GIT_REV := $(shell git rev-parse --short HEAD || echo UNKOWN)
 OBJS = kernel/version_$(GIT_REV).o
 
-ABCREV = 0f9e5488ced3
+ABCREV = 766d323095c4
 ABCPULL = 1
 
 -include Makefile.conf

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index c539dd17db96edc63dff492e6dbfdb457f162339..e37f896f205efd9f2d2ecd4bbf6fe20cf1fc5b66 100644 (file)
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -327,7 +327,7 @@ static void handle_loops()
                fclose(dot_f);
 }
 
-static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, bool cleanup, int lut_mode)
+static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode)
 {
        module = current_module;
        map_autoidx = RTLIL::autoidx++;
@@ -455,11 +455,19 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 
                char buffer[1024];
                int buffer_pos = 0;
-               if (!liberty_file.empty())
+               if (!liberty_file.empty()) {
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
-                                       "%s -s -c 'read_verilog %s/input.v; read_liberty %s; map; ",
+                                       "%s -s -c 'read_verilog %s/input.v; read_lib %s; ",
                                        exe_file.c_str(), tempdir_name, liberty_file.c_str());
-               else
+                       if (!constr_file.empty())
+                               buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
+                                               "read_constr %s; ", constr_file.c_str());
+                       buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
+                                       "strash; balance; dch; map; topo; ");
+                       if (!constr_file.empty())
+                               buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
+                                               "buffer; upsize; dnsize; stime; ");
+               } else
                if (!script_file.empty())
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
                                        "%s -s -c 'read_verilog %s/input.v; source %s; ",
@@ -467,11 +475,11 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                else
                if (lut_mode)
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
-                                       "%s -s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; if; ",
+                                       "%s -s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; strash; balance; dch; if; ",
                                        exe_file.c_str(), tempdir_name, tempdir_name);
                else
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
-                                       "%s -s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; map; ",
+                                       "%s -s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; strash; balance; dch; map; ",
                                        exe_file.c_str(), tempdir_name, tempdir_name);
                if (lut_mode)
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_blif %s/output.blif' 2>&1", tempdir_name);
@@ -694,6 +702,9 @@ struct AbcPass : public Pass {
                log("        but keeps using yosys's internal gate library. This option is ignored if\n");
                log("        the -script option is also used.\n");
                log("\n");
+               log("    -constr <file>\n");
+               log("        pass this file with timing constraints to ABC\n");
+               log("\n");
                log("    -lut <width>\n");
                log("        generate netlist using luts of (max) the specified width.\n");
                log("\n");
@@ -713,7 +724,7 @@ struct AbcPass : public Pass {
                log_push();
 
                std::string exe_file = rewrite_yosys_exe("yosys-abc");
-               std::string script_file, liberty_file;
+               std::string script_file, liberty_file, constr_file;
                bool cleanup = true;
                int lut_mode = 0;
 
@@ -725,18 +736,24 @@ struct AbcPass : public Pass {
                                exe_file = args[++argidx];
                                continue;
                        }
-                       if (arg == "-script" && argidx+1 < args.size() && liberty_file.empty()) {
+                       if (arg == "-script" && argidx+1 < args.size() && liberty_file.empty() && constr_file.empty()) {
                                script_file = args[++argidx];
                                if (!script_file.empty() && script_file[0] != '/')
                                        script_file = std::string(pwd) + "/" + script_file;
                                continue;
                        }
-                       if (arg == "-liberty" && argidx+1 < args.size() && script_file.empty()) {
+                       if (arg == "-liberty" && argidx+1 < args.size() && script_file.empty() && liberty_file.empty()) {
                                liberty_file = args[++argidx];
                                if (!liberty_file.empty() && liberty_file[0] != '/')
                                        liberty_file = std::string(pwd) + "/" + liberty_file;
                                continue;
                        }
+                       if (arg == "-constr" && argidx+1 < args.size() && script_file.empty() && constr_file.empty()) {
+                               constr_file = args[++argidx];
+                               if (!constr_file.empty() && constr_file[0] != '/')
+                                       constr_file = std::string(pwd) + "/" + constr_file;
+                               continue;
+                       }
                        if (arg == "-lut" && argidx+1 < args.size() && lut_mode == 0) {
                                lut_mode = atoi(args[++argidx].c_str());
                                continue;
@@ -755,7 +772,7 @@ struct AbcPass : public Pass {
                                if (mod_it.second->processes.size() > 0)
                                        log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
                                else
-                                       abc_module(design, mod_it.second, script_file, exe_file, liberty_file, cleanup, lut_mode);
+                                       abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode);
                        }
 
                assign_map.clear();

diff --git a/techlibs/cmos/cmos_cells.lib b/techlibs/cmos/cmos_cells.lib
index 164256c0184bc271436f89aef8b6ab45f1650f1c..697d8205cfd1cf21ebed47ec89515823db161205 100644 (file)
--- a/techlibs/cmos/cmos_cells.lib
+++ b/techlibs/cmos/cmos_cells.lib
@@ -1,4 +1,10 @@
 library(demo) {
+  cell(BUF) {
+    area: 6;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
   cell(NOT) {
     area: 3;
     pin(A) { direction: input; }

diff --git a/techlibs/cmos/cmos_cells.sp b/techlibs/cmos/cmos_cells.sp
index cb94caa23238ff145ce1332815b137fbfbaa4e8d..673b20d0824035b7d8566485fec778aa926d6c2d 100644 (file)
--- a/techlibs/cmos/cmos_cells.sp
+++ b/techlibs/cmos/cmos_cells.sp
@@ -1,4 +1,9 @@
 
+.SUBCKT BUF A Y
+X1 A B NOT
+X2 B Y NOT
+.ENDS NOT
+
 .SUBCKT NOT A Y
 M1 Y A Vdd Vdd cmosp L=1u W=10u
 M2 Y A Vss Vss cmosn L=1u W=10u