arch: Get rid of the unused type AnyReg.

This type is defined for all the ISAs but isn't used by anything.

Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8
Reviewed-on: https://gem5-review.googlesource.com/c/13539
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 151ea7d7c444b5eb0780351978b3ae22411a0159..53ade4719e0663a16b90892af6cd22d38a3ea80c 100644 (file)
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -66,13 +66,6 @@ using VecRegContainer = VecReg::Container;
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-union AnyReg
-{
-    IntReg  intreg;
-    FloatReg   fpreg;
-    MiscReg ctrlreg;
-};
-
 enum MiscRegIndex
 {
     MISCREG_FPCR = NumInternalProcRegs,

diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 0a617e4dca9a3b31e45c7ba291d4fb28605a0957..e7defd1824061eba0c8efd060dce88b17126568a 100644 (file)
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -119,13 +119,6 @@ const int SyscallNumReg = ReturnValueReg;
 const int SyscallPseudoReturnReg = ReturnValueReg;
 const int SyscallSuccessReg = ReturnValueReg;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    CCReg    ccreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 } // namespace ArmISA
 
 #endif

diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index b44283d35dc985e34e78438c7fb9ca0f76de2f34..55c2dee034e441e7c035f7a24caad87a916dc14d 100644 (file)
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -299,12 +299,6 @@ using VecRegContainer = VecReg::Container;
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 } // namespace MipsISA
 
 #endif

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 4e8c9e9f4dc714e5872471a19765daa524fd5872..adbaae539f87e0690acf97f9ff9cf49ecc1bbb20 100644 (file)
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -95,12 +95,6 @@ const int SyscallNumReg = 0;
 const int SyscallPseudoReturnReg = 3;
 const int SyscallSuccessReg = 3;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 enum MiscIntRegNums {
     INTREG_CR = NumIntArchRegs,
     INTREG_XER,

diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 596fdf4d0f212380946c9f1e717f18b2b1bd4423..a7f4d2a152afbb8c4d78419a7b0eac70573afc60 100644 (file)
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -62,13 +62,6 @@ using VecRegContainer = VecReg::Container;
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-typedef union
-{
-    IntReg intReg;
-    FloatReg fpreg;
-    MiscReg ctrlreg;
-} AnyReg;
-
 // semantically meaningful register indices
 const int ZeroReg = 0;      // architecturally meaningful
 // the rest of these depend on the ABI

diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 9db3349f07f8cd6256d1189297692414e3360bf5..c2977f8a2b3863e763e542f3ad7417141249b7e6 100644 (file)
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -107,13 +107,6 @@ constexpr unsigned NumVecRegs = 1;
 //technically for x87 (80 bits) or at all for xmm (128 bits)
 typedef double FloatReg;
 typedef uint64_t FloatRegBits;
-typedef union
-{
-    IntReg intReg;
-    FloatReg fpReg;
-    CCReg ccReg;
-    MiscReg ctrlReg;
-} AnyReg;
 
 } // namespace X86ISA