Update abc_* attr in ecp5 and ice40

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 3d343b31503580cec51aac8ee7063cec25009411..864a3550feb41e6b3ee4d97dc59c37daecc5a469 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
-module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
-                  output S0, S1, COUT);
-
+(* abc_box_id=1, lib_whitebox *)
+module CCU2C(
+       (* abc_carry_in *) input CIN,
+       input  A0, B0, C0, D0, A1, B1, C1, D1,
+       output S0, S1,
+       (* abc_carry_out *) output COUT
+);
        parameter [15:0] INIT0 = 16'h0000;
        parameter [15:0] INIT1 = 16'h0000;
        parameter INJECT1_0 = "YES";
@@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
+//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-       input [3:0] DI,
-       input [3:0] WAD,
-       input WRE, WCK,
-       input [3:0] RAD,
+       (* abc_scc_break *) input [3:0] DI,
+       (* abc_scc_break *) input [3:0] WAD,
+       (* abc_scc_break *) input       WRE,
+       input        WCK,
+       input  [3:0] RAD,
        output [3:0] DO
 );
        parameter WCKMUX = "WCK";

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 2205be27d39caff95e8ce815621297c2dd51ebe9..5b18fec27d929c8ab3d792f55cc51e88fa69b986 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
        assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
-module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+(* abc_box_id = 1, lib_whitebox *)
+module \$__ICE40_FULL_ADDER (
+       (* abc_carry_out *) output CO,
+       output O,
+       input A,
+       input B,
+       (* abc_carry_in *) input CI
+);
        SB_CARRY carry (
                .I0(A),
                .I1(B),