attempt to fix tables

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 28acbf1bc0ac74d24c7e824420d2819091d16ea3..4a97a6a7f4795adbbd4686139ab0cd6826bc0a6f 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -82,6 +82,7 @@ Standard PowerISA Integer registers are aliased to some of the SV integer regist
 ## Floating-Point Registers
 
 Standard PowerISA floating-point and VSX registers are aliased to some of the SV floating-point registers:
+
 | FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register |
 |-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|
 | FPR\[0\]        | VSR\[0\]\.dword\[0\]  | SVFR0\_00          | FPR\[8\]        | VSR\[8\]\.dword\[0\]  | SVFR8\_00          | FPR\[16\]       | VSR\[16\]\.dword\[0\] | SVFR16\_00         | FPR\[24\]       | VSR\[24\]\.dword\[0\] | SVFR24\_00         |