radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING

Copied from PAL. Higher values break tessellation, which I was only able
to reproduce with register shadowing enabled.

Fixes: 0bf3e6fae7f82b4f16fbcbb05a1ae47f7930e189 "radeonsi/gfx10: double the number of tessellation offchip buffers per SE"
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 46f2ff724920c6444b5a804506d3a357e0fcc7ec..9501cb7c12364ba32f170a378f292083db5dccd6 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1081,7 +1081,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
    unsigned max_offchip_buffers_per_se;
 
    if (sscreen->info.chip_class >= GFX10)
-      max_offchip_buffers_per_se = 256;
+      max_offchip_buffers_per_se = 128;
    /* Only certain chips can use the maximum value. */
    else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20)
       max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;