[Patch AArch64] Add support for Cortex-A35

gcc/

	* config/aarch64/aarch64-cores.def (cortex-a35): New.
	* config/aarch64/aarch64.c (cortexa35_tunings): New.
	* config/aarch64/aarch64-tune.md: Regenerate.
	* doc/invoke.texi (-mcpu): Add Cortex-A35

From-SVN: r230458

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6316ab6d122699379813284a657a23b77015b795..7616daeb01900296562d3aba915e01102984ac02 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-11-17  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * config/aarch64/aarch64-cores.def (cortex-a35): New.
+       * config/aarch64/aarch64.c (cortexa35_tunings): New.
+       * config/aarch64/aarch64-tune.md: Regenerate.
+       * doc/invoke.texi (-mcpu): Add Cortex-A35
+
 2015-11-17  Venkataramanan Kumar  <Venkataramanan.Kumar@amd.com>
 
        * tree-if-conv.c: Include varasm.h

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 4af70ca613c8d1ff550fed01b1f86f59dd545fa1..f8fab28d9120ca854f0d8f77dcf17487cb8855df 100644 (file)
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -40,6 +40,7 @@
 
 /* V8 Architecture Processors.  */
 
+AARCH64_CORE("cortex-a35",  cortexa35, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, "0x41", "0xd04")
 AARCH64_CORE("cortex-a53",  cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, "0x41", "0xd03")
 AARCH64_CORE("cortex-a57",  cortexa57, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07")
 AARCH64_CORE("cortex-a72",  cortexa72, cortexa57, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08")

diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index c65a12420ad8f3263e7f30ba3c763d99688c52c5..cbc6f4879edb2f3842a50dfafe206313d49e9cf8 100644 (file)
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-       "cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
+       "cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
        (const (symbol_ref "((enum attr_tune) aarch64_tune)")))

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 96df9ed19e9069ce0bde9861cd7420af0b7ab367..54b9b4210fae4cc7ff00378bc55328ec112e9125 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -369,6 +369,31 @@ static const struct tune_params generic_tunings =
   (AARCH64_EXTRA_TUNE_NONE)    /* tune_flags.  */
 };
 
+static const struct tune_params cortexa35_tunings =
+{
+  &cortexa53_extra_costs,
+  &generic_addrcost_table,
+  &cortexa53_regmove_cost,
+  &generic_vector_cost,
+  &generic_branch_cost,
+  4, /* memmov_cost  */
+  1, /* issue_rate  */
+  (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+   | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR), /* fusible_ops  */
+  8,   /* function_align.  */
+  8,   /* jump_align.  */
+  4,   /* loop_align.  */
+  2,   /* int_reassoc_width.  */
+  4,   /* fp_reassoc_width.  */
+  1,   /* vec_reassoc_width.  */
+  2,   /* min_div_recip_mul_sf.  */
+  2,   /* min_div_recip_mul_df.  */
+  0,   /* max_case_values.  */
+  0,   /* cache_line_size.  */
+  tune_params::AUTOPREFETCHER_WEAK,    /* autoprefetcher_model.  */
+  (AARCH64_EXTRA_TUNE_NONE)    /* tune_flags.  */
+};
+
 static const struct tune_params cortexa53_tunings =
 {
   &cortexa53_extra_costs,

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9ecdf266603c0d901c4439007fa7e31d79805a48..73b758240f32d36076b7339b9f449d36d8c2cb0b 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12590,8 +12590,9 @@ processors implementing the target architecture.
 @opindex mtune
 Specify the name of the target processor for which GCC should tune the
 performance of the code.  Permissible values for this option are:
-@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
-@samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx}, @samp{xgene1}.
+@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
+@samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx},
+@samp{xgene1}.
 
 Additionally, this option can specify that GCC should tune the performance
 of the code for a big.LITTLE system.  Permissible values for this