add batch of instructions from

https://bugs.libre-soc.org/show_bug.cgi?id=917#c25

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 8b68ecc122ea2097a2a2072ab70ecff930aacc08..d730582bf1aaac2b6c86595a62aef02c4688221f 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -81,6 +81,81 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_7_batch(self):
+        "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
+        expected = [
+                    "addis 2,12,0",
+                    "addi 2,2,0",
+                    "addis 9,2,0",
+                    "addi 9,9,0",
+                    "rlwinm 7,7,2,0,29",
+                    "mulli 0,7,31",
+                    "add 10,6,0",
+                    "setvl 0,0,8,1,1,0",
+                    "addi 16,4,124",
+                    "lfiwax 0,0,5",
+                    "addi 5,3,64",
+                    "sv.lfs *32,256(4)",
+                    "sv.lfs *40,256(5)",
+                    "sv.fmuls *32,*32,*40",
+                    "sv.fadds 0,*32,0",
+                    "addi 5,3,192",
+                    "addi 4,4,128",
+                    "sv.lfs *32,256(4)",
+                    "sv.lfs *40,256(5)",
+                    "sv.fmuls *32,*32,*40",
+                    "sv.fsubs 0,0,*32",
+                    "addi 4,4,65408",
+                    "stfs 0,0(6)",
+                    "add 6,6,7",
+                    "addi 4,4,4",
+                    "addi 0,0,15",
+                    "mtspr 288,0",
+                    "addi 8,0,4",
+                    "lfiwax 0,0,9",
+                    "lfiwax 1,0,9",
+                    "addi 5,3,64",
+                    "add 5,5,8",
+                    "sv.lfs *32,256(5)",
+                    "sv.lfs *40,256(4)",
+                    "sv.lfs *48,256(16)",
+                    "sv.fmuls *40,*32,*40",
+                    "sv.fadds 0,0,*40",
+                    "sv.fmuls *32,*32,*48",
+                    "sv.fsubs 1,1,*32",
+                    "addi 5,3,192",
+                    "subf 5,8,5",
+                    "addi 4,4,128",
+                    "addi 16,16,128",
+                    "sv.lfs *32,256(5)",
+                    "sv.lfs *40,256(4)",
+                    "sv.lfs *48,256(16)",
+                    "sv.fmuls *40,*32,*40",
+                    "sv.fsubs 0,0,*40",
+                    "sv.fmuls *32,*32,*48",
+                    "sv.fsubs 1,1,*32",
+                    "addi 4,4,65408",
+                    "addi 16,16,65408",
+                    "stfs 0,0(6)",
+                    "add 6,6,7",
+                    "stfs 1,0(10)",
+                    "subf 10,7,10",
+                    "addi 8,8,4",
+                    "addi 4,4,4",
+                    "addi 16,16,65532",
+                    "bc 16,0,0xff4c",
+                    "addi 5,3,128",
+                    "addi 4,4,128",
+                    "lfiwax 0,0,9",
+                    "sv.lfs *32,256(4)",
+                    "sv.lfs *40,256(5)",
+                    "sv.fmuls *32,*32,*40",
+                    "sv.fsubs 0,0,*32",
+                    "stfs 0,0(6)",
+                    "bclr 20,0,0",
+                        ]
+        self._do_tst(expected)
+
 if __name__ == "__main__":
     unittest.main()