verific: allow memories to be inferred in loops (vhdl)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b53bad7dace41e368b67991d9b94c023a02b4746..284d5db31f6374648426acb6a44e61e672881873 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2553,6 +2553,7 @@ struct VerificPass : public Pass {
 #ifdef VERIFIC_VHDL_SUPPORT
                        RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
                        RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
+                       RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1);
 
                        RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
                        RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);