Fixed typo in last commit
authorAndrew Zonenberg <azonenberg@drawersteak.com>
Wed, 19 Oct 2016 03:46:49 +0000 (20:46 -0700)
committerAndrew Zonenberg <azonenberg@drawersteak.com>
Wed, 19 Oct 2016 03:46:49 +0000 (20:46 -0700)
techlibs/greenpak4/cells_sim.v

index 76bf058d27c0ed14501e1c849005f66f546b5556..80746be0fd3ae8e4d8ff3a06b520bb3f760720cd 100644 (file)
@@ -308,7 +308,7 @@ endmodule
 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
        initial OUT = 0;
        parameter PATTERN_DATA = 16'h0;
-       parameter PATTERN_LEN = 4'd16;
+       parameter PATTERN_LEN = 5'd16;
 
        reg[3:0] count = 0;
        always @(posedge CLK) begin