Timing cache works for hello world test.

Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))

src/cpu/simple/timing.cc:
    Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
    Handle marking MSHR's in service
    Add support for getting CSHR's
src/mem/cache/base_cache.hh:
    Make these functions visible at the base cache level
src/mem/cache/cache.hh:
    make the functions virtual
src/mem/cache/cache_impl.hh:
    Rename the function to make sense
src/mem/packet.hh:
    Accidentally clearing the needsResponse field when sending a response back.

--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ad04c8d3bd639ae7d6bae221e27c16a5719db9d0..036037ba9a0339f6bfa347b0cb63d8a496ba8684 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -451,7 +451,12 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    cpu->completeIfetch(pkt);
+    if (cpu->_status == DcacheWaitResponse)
+        cpu->completeDataAccess(pkt);
+    else if (cpu->_status == IcacheWaitResponse)
+        cpu->completeIfetch(pkt);
+    else
+        assert("OOPS" && 0);
     return true;
 }
 

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 15a21efa1bd7c90dd32d0828326bad185225e423..4fbda4074514094c3c7a2283752a3707fcbafadb 100644 (file)
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -118,9 +118,15 @@ BaseCache::CacheEvent::process()
     {
         if (!cachePort->isCpuSide)
             pkt = cachePort->cache->getPacket();
-        //Else get coherence req
+        else
+            pkt = cachePort->cache->getCoherencePacket();
+        bool success = cachePort->sendTiming(pkt);
+        cachePort->cache->sendResult(pkt, success);
+        return;
     }
-    cachePort->sendTiming(pkt);
+    //Know the packet to send, no need to mark in service (must succed)
+    bool success = cachePort->sendTiming(pkt);
+    assert(success);
 }
 
 const char *

diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 5370a73c8ff285d9378905c588c31a28c67d9248..f832735dbe75b9b29d06ede7145cbb6d7cb18e71 100644 (file)
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -153,6 +153,17 @@ class BaseCache : public MemObject
         fatal("No implementation");
     }
 
+    virtual Packet *getCoherencePacket()
+    {
+        fatal("No implementation");
+    }
+
+    virtual void sendResult(Packet* &pkt, bool success)
+    {
+
+        fatal("No implementation");
+    }
+
     /**
      * Bit vector of the blocking reasons for the access path.
      * @sa #BlockedCause

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 2e77444a08cccd5e654bfc7045e5ed3a34743a14..ec5b800a8e74e90145fe5dd707e28e71ff76ef75 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -175,7 +175,7 @@ class Cache : public BaseCache
      * @param req The request.
      * @param success True if the request was sent successfully.
      */
-    void sendResult(Packet * &pkt, bool success);
+    virtual void sendResult(Packet * &pkt, bool success);
 
     /**
      * Handles a response (cache line fill/write ack) from the bus.
@@ -202,7 +202,7 @@ class Cache : public BaseCache
      * Selects a coherence message to forward to lower levels of the hierarchy.
      * @return The coherence message to forward.
      */
-    Packet * getCoherenceReq();
+    virtual Packet * getCoherencePacket();
 
     /**
      * Snoops bus transactions to maintain coherence.

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index aae5cbf018a7f176ff6ef74d5aee5b13a1698bf2..a447ae3d589d53275462eb008b65f184e0fecc57 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -350,7 +350,7 @@ Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 
 template<class TagStore, class Buffering, class Coherence>
 Packet *
-Cache<TagStore,Buffering,Coherence>::getCoherenceReq()
+Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 {
     return coherence->getPacket();
 }

diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 2b97ab0c1de715e32396ee44407e3b1e4832bcc2..1325dfc5b8e65279afdfa34b52c0f3eb540e4b9e 100644 (file)
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -183,19 +183,19 @@ class Packet
         ReadReq                = IsRead  | IsRequest | NeedsResponse,
         WriteReq       = IsWrite | IsRequest | NeedsResponse,
         WriteReqNoAck  = IsWrite | IsRequest,
-        ReadResp       = IsRead  | IsResponse,
-        WriteResp      = IsWrite | IsResponse,
+        ReadResp       = IsRead  | IsResponse | NeedsResponse,
+        WriteResp      = IsWrite | IsResponse | NeedsResponse,
         Writeback       = IsWrite | IsRequest,
         SoftPFReq       = IsRead  | IsRequest | IsSWPrefetch | NeedsResponse,
         HardPFReq       = IsRead  | IsRequest | IsHWPrefetch | NeedsResponse,
-        SoftPFResp      = IsRead  | IsRequest | IsSWPrefetch | IsResponse,
-        HardPFResp      = IsRead  | IsRequest | IsHWPrefetch | IsResponse,
+        SoftPFResp      = IsRead  | IsResponse | IsSWPrefetch | NeedsResponse,
+        HardPFResp      = IsRead  | IsResponse | IsHWPrefetch | NeedsResponse,
         InvalidateReq   = IsInvalidate | IsRequest,
         WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
-        UpgradeReq      = IsInvalidate | NeedsResponse,
-        UpgradeResp     = IsInvalidate | IsResponse,
-        ReadExReq       = IsRead | IsInvalidate | NeedsResponse,
-        ReadExResp      = IsRead | IsInvalidate | IsResponse
+        UpgradeReq      = IsInvalidate | IsRequest | NeedsResponse,
+        UpgradeResp     = IsInvalidate | IsResponse | NeedsResponse,
+        ReadExReq       = IsRead | IsInvalidate | IsRequest | NeedsResponse,
+        ReadExResp      = IsRead | IsInvalidate | IsResponse | NeedsResponse
     };
 
     /** Return the string name of the cmd field (for debugging and
@@ -311,8 +311,9 @@ class Packet
      *   should not be called. */
     void makeTimingResponse() {
         assert(needsResponse());
+        assert(isRequest());
         int icmd = (int)cmd;
-        icmd &= ~(IsRequest | NeedsResponse);
+        icmd &= ~(IsRequest);
         icmd |= IsResponse;
         cmd = (Command)icmd;
         dest = src;