soc/cores/uart remove software (will be re-written and will move to soc/tools)

diff --git a/litex/soc/cores/uart/software/__init__.py b/litex/soc/cores/uart/software/__init__.py
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/litex/soc/cores/uart/software/csr.py b/litex/soc/cores/uart/software/csr.py
deleted file mode 100644 (file)
index 0cf706d..0000000
--- a/litex/soc/cores/uart/software/csr.py
+++ /dev/null
@@ -1,78 +0,0 @@
-import csv
-
-# TODO: move
-
-class MappedReg:
-    def __init__(self, readfn, writefn, name, addr, length, busword, mode):
-        self.readfn = readfn
-        self.writefn = writefn
-        self.addr = addr
-        self.length = length
-        self.busword = busword
-        self.mode = mode
-
-    def read(self):
-        if self.mode not in ["rw", "ro"]:
-            raise KeyError(name + "register not readable")
-        datas = self.readfn(self.addr, burst_length=self.length)
-        if isinstance(datas, int):
-            return datas
-        else:
-            data = 0
-            for i in range(self.length):
-                data = data << self.busword
-                data |= datas[i]
-            return data
-
-    def write(self, value):
-        if self.mode not in ["rw", "wo"]:
-            raise KeyError(name + "register not writable")
-        datas = []
-        for i in range(self.length):
-            datas.append((value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1))
-        self.writefn(self.addr, datas)
-
-
-class MappedElements:
-    def __init__(self, d):
-        self.d = d
-
-    def __getattr__(self, attr):
-        try:
-            return self.__dict__['d'][attr]
-        except KeyError:
-            pass
-        raise KeyError("No such element " + attr)
-
-
-def build_csr_bases(addrmap):
-    csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
-    d = {}
-    for item in csv_reader:
-        group, name, addr, dummy0, dummy1 = item
-        if group == "csr_base":
-            d[name] = int(addr.replace("0x", ""), 16)
-    return MappedElements(d)
-
-def build_csr_registers(addrmap, busword, readfn, writefn):
-    csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
-    d = {}
-    for item in csv_reader:
-        group, name, addr, length, mode = item
-        if group == "csr_register":
-            addr = int(addr.replace("0x", ""), 16)
-            length = int(length)
-            d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
-    return MappedElements(d)
-
-def build_constants(addrmap):
-    csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
-    d = {}
-    for item in csv_reader:
-        group, name, value, dummy0, dummy1 = item
-        if group == "constant":
-            try:
-                d[name] = int(value)
-            except:
-                d[name] = value
-    return MappedElements(d)

diff --git a/litex/soc/cores/uart/software/wishbone.py b/litex/soc/cores/uart/software/wishbone.py
deleted file mode 100644 (file)
index 8e9e7fc..0000000
--- a/litex/soc/cores/uart/software/wishbone.py
+++ /dev/null
@@ -1,78 +0,0 @@
-import serial
-from struct import *
-
-from litex.soc.cores.uart.software.csr import *
-
-
-def write_b(uart, data):
-    uart.write(pack('B', data))
-
-
-class UARTWishboneBridgeDriver:
-    cmds = {
-        "write": 0x01,
-        "read":  0x02
-    }
-    def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
-        self.port = port
-        self.baudrate = str(baudrate)
-        self.debug = debug
-        self.uart = serial.Serial(port, baudrate, timeout=0.25)
-        if addrmap is not None:
-            self.bases = build_csr_bases(addrmap)
-            self.regs = build_csr_registers(addrmap, busword, self.read, self.write)
-            self.constants = build_constants(addrmap)
-
-    def open(self):
-        self.uart.flushOutput()
-        self.uart.close()
-        self.uart.open()
-        self.uart.flushInput()
-
-    def close(self):
-        self.uart.flushOutput()
-        self.uart.close()
-
-    def read(self, addr, burst_length=1):
-        datas = []
-        self.uart.flushInput()
-        write_b(self.uart, self.cmds["read"])
-        write_b(self.uart, burst_length)
-        word_addr = addr//4
-        write_b(self.uart, (word_addr >> 24) & 0xff)
-        write_b(self.uart, (word_addr >> 16) & 0xff)
-        write_b(self.uart, (word_addr >>  8) & 0xff)
-        write_b(self.uart, (word_addr >>  0) & 0xff)
-        for i in range(burst_length):
-            data = 0
-            for k in range(4):
-                data = data << 8
-                data |= ord(self.uart.read())
-            if self.debug:
-                print("RD {:08X} @ {:08X}".format(data, addr + 4*i))
-            datas.append(data)
-        if burst_length == 1:
-            return datas[0]
-        else:
-            return datas
-
-    def write(self, addr, data):
-        if isinstance(data, list):
-            burst_length = len(data)
-        else:
-            burst_length = 1
-            data = [data]
-        write_b(self.uart, self.cmds["write"])
-        write_b(self.uart, burst_length)
-        word_addr = addr//4
-        write_b(self.uart, (word_addr >> 24) & 0xff)
-        write_b(self.uart, (word_addr >> 16) & 0xff)
-        write_b(self.uart, (word_addr >>  8) & 0xff)
-        write_b(self.uart, (word_addr >>  0) & 0xff)
-        for i in range(len(data)):
-            dat = data[i]
-            for j in range(4):
-                write_b(self.uart, (dat >> 24) & 0xff)
-                dat = dat << 8
-            if self.debug:
-                print("WR {:08X} @ {:08X}".format(data[i], addr + 4*i))