All Rights Reserved
-M5 compiled Nov 15 2010 00:04:22
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 15 2010 00:10:23
+M5 compiled Dec 2 2010 15:11:52
+M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
+M5 started Dec 3 2010 12:08:56
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 601454696500 because target called exit()
+Exiting @ tick 601459170500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 179682 # Simulator instruction rate (inst/s)
-host_mem_usage 208000 # Number of bytes of host memory used
-host_seconds 7822.74 # Real time elapsed on the host
-host_tick_rate 76885423 # Simulator tick rate (ticks/s)
+host_inst_rate 193964 # Simulator instruction rate (inst/s)
+host_mem_usage 208068 # Number of bytes of host memory used
+host_seconds 7246.73 # Real time elapsed on the host
+host_tick_rate 82997346 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405604152 # Number of instructions simulated
-sim_seconds 0.601455 # Number of seconds simulated
-sim_ticks 601454696500 # Number of ticks simulated
+sim_seconds 0.601459 # Number of seconds simulated
+sim_ticks 601459170500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 98804348 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 100538146 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 98804477 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 100538318 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 5348299 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 105812900 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 105812900 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 5348297 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 105813048 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 105813048 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 21328327 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 21327804 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1172134111 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.270779 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.680126 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1172142474 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.270770 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.680117 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 418023744 35.66% 35.66% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 498322579 42.51% 78.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 52995965 4.52% 82.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 103673250 8.84% 91.54% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 32915504 2.81% 94.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 8294294 0.71% 95.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 418030495 35.66% 35.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 498323128 42.51% 78.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 52996990 4.52% 82.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 103673808 8.84% 91.54% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 32915552 2.81% 94.35% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 8294277 0.71% 95.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19% 97.25% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 10946246 0.93% 98.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 21328327 1.82% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 10946218 0.93% 98.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 21327804 1.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1172134111 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1172142474 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489523295 # Number of instructions committed
system.cpu.commit.COM:loads 402512844 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569360986 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5348299 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 5348297 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 219352878 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 219358956 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
-system.cpu.cpi 0.855795 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.855795 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 295701747 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14658.100936 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.537350 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 294883428 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 11995002500 # number of ReadReq miss cycles
+system.cpu.cpi 0.855802 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.855802 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 295702053 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14658.341236 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.553744 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 294883757 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 11994862000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 818319 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 604827 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1593832500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 818296 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 604804 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1593836000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 213492 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency 267000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 15552.165643 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.834160 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 165080576 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 27468857045 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 15552.195709 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.845351 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 165080578 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 27468879045 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010586 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1766240 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1498175 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3438425299 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses 1766238 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1498173 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3438428299 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 955.148896 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 955.149583 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 462548563 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 15269.088284 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 10449.973314 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 459964004 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 39463859545 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses 462548869 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 15269.190131 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 10449.986812 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 459964335 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 39463741045 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005588 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2584559 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2103002 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5032257799 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_misses 2584534 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2102977 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5032264299 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 481557 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999860 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.424781 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 462548563 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 15269.088284 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 10449.973314 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999859 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.424423 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 462548869 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 15269.190131 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 10449.986812 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 459964004 # number of overall hits
-system.cpu.dcache.overall_miss_latency 39463859545 # number of overall miss cycles
+system.cpu.dcache.overall_hits 459964335 # number of overall hits
+system.cpu.dcache.overall_miss_latency 39463741045 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005588 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2584559 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2103002 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5032257799 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_misses 2584534 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2102977 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5032264299 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 481557 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 477468 # number of replacements
system.cpu.dcache.sampled_refs 481564 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.424781 # Cycle average of tags in use
-system.cpu.dcache.total_refs 459965323 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 132220000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse 4095.424423 # Cycle average of tags in use
+system.cpu.dcache.total_refs 459965654 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 132275000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 428419 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 393630434 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 1750728609 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 405694605 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 351105685 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 30409425 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 21703387 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 105812900 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 173095521 # Number of cache lines fetched
-system.cpu.fetch.Cycles 548231197 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1429406 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 1755969057 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 6170035 # Number of cycles fetch has spent squashing
+system.cpu.decode.DECODE:BlockedCycles 393632662 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 1750743114 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 405697797 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 351108016 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 30410707 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 21703388 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 105813048 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 173096808 # Number of cache lines fetched
+system.cpu.fetch.Cycles 548235409 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1429410 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1755979749 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 6170644 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 173095521 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 98804348 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.459768 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1202543536 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.699989 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 173096808 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 98804477 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.459766 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 1202552570 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.464003 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.699994 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 827407907 68.80% 68.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 82886631 6.89% 75.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 45822474 3.81% 79.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22740031 1.89% 81.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 33832186 2.81% 84.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 32824396 2.73% 86.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 14991772 1.25% 88.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 7935570 0.66% 88.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 134102569 11.15% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 827414016 68.80% 68.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 82887160 6.89% 75.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 45822502 3.81% 79.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22740112 1.89% 81.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 32824408 2.73% 86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 14992288 1.25% 88.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7935666 0.66% 88.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 134104221 11.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1202543536 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 173095521 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35040.947075 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35056.370656 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 173093726 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 62898500 # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total 1202552570 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 173096808 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35071.906355 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35057.573416 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 173095014 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 62919000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1795 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses 1794 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 45398000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 45364500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 1295 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 1294 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.icache.demand_avg_miss_latency 35040.947075 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35056.370656 # average overall mshr miss latency
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system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1795 # number of demand (read+write) misses
+system.cpu.icache.demand_misses 1794 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 45398000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 1295 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1795 # number of overall misses
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system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 45398000 # number of overall MSHR miss cycles
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-system.cpu.icache.overall_mshr_misses 1295 # number of overall MSHR misses
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system.cpu.icache.replacements 158 # number of replacements
-system.cpu.icache.sampled_refs 1294 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1044.146064 # Cycle average of tags in use
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
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-system.cpu.iew.EXEC:branches 89387994 # Number of branches executed
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system.cpu.iew.WB:fanout 0.958320 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1161633451 # num instructions producing a value
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-system.cpu.iew.WB:sent 1473866323 # cumulative count of insts sent to commit
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 9806 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 124904325 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread.0.ignoredResponses 7473 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled
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system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 648511 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.168504 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.168504 # IPC: Total IPC of All Threads
+system.cpu.ipc 1.168495 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.168495 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618266 0.18% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::MemRead 423845993 28.60% 88.48% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst)
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system.cpu.iq.ISSUE:fu_full::IntAlu 213199 6.57% 6.57% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::7 226814 0.02% 99.99% # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:rate 1.231951 # Inst issue rate
-system.cpu.iq.iqInstsAdded 1603622713 # Number of instructions added to the IQ (excludes non-spec)
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-system.cpu.iq.iqNonSpecInstsAdded 3075375 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 200589396 # Number of squashed instructions iterated over during squash; mainly for profiling
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-system.cpu.iq.iqSquashedNonSpecRemoved 831704 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 279090439 # Number of squashed operands that are examined and possibly removed from graph
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+system.cpu.iq.iqSquashedOperandsExamined 279093413 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.656689 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.323632 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.623615 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.356706 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 2080631000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893879500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893881500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 214779 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34036.266738 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_miss_rate 0.156817 # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency 1044278000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156817 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.Writeback_accesses 428419 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 428419 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 482859 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 3227006500 # number of demand (read+write) miss cycles
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-system.cpu.l2cache.demand_misses 94151 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 3226973500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.194985 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 94150 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2938157500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.194987 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 94151 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 2938130000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.194985 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 94150 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.060603 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::0 0.060598 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1985.832482 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15675.625212 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 482859 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34274.797931 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.864505 # average overall mshr miss latency
+system.cpu.l2cache.occ_blocks::0 1985.675951 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15675.618394 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 482858 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34274.811471 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.903877 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 388708 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3227006500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.194987 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 94151 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 3226973500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.194985 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 94150 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2938157500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.194987 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 94151 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 2938130000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.194985 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 94150 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 75917 # number of replacements
-system.cpu.l2cache.sampled_refs 91431 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 75916 # number of replacements
+system.cpu.l2cache.sampled_refs 91430 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17661.457694 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 467629 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 17661.294345 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 467627 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 59275 # number of writebacks
-system.cpu.memDep0.conflictingLoads 406523725 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 165664801 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 468103706 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 188277007 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 1202909394 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 123850376 # Number of cycles rename is blocking
+system.cpu.memDep0.conflictingLoads 406523724 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 165665166 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 468104287 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 188277603 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 1202918342 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 123850375 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers
-system.cpu.rename.RENAME:IQFullEvents 134234500 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 443697356 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 41034725 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IQFullEvents 134234499 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 443701080 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 41034727 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 2926103966 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 1732026812 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 1445187078 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 329587648 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 30409425 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 217220624 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 200416626 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 57778107 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 3036469 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 385260528 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 3035800 # count of temporary serializing insts renamed
-system.cpu.timesIdled 11398 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:RenameLookups 2926118072 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 1732032872 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 1445195761 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 329589448 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 30410707 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 217220623 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 200425309 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 57780337 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 385268433 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed
+system.cpu.timesIdled 11396 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Nov 14 2010 23:49:18
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 14 2010 23:51:27
+M5 compiled Dec 1 2010 12:54:21
+M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
+M5 started Dec 3 2010 12:06:07
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 118370500
-Exiting @ tick 1900844230500 because m5_exit instruction encountered
+Exiting @ tick 1900831708500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 136464 # Simulator instruction rate (inst/s)
-host_mem_usage 294032 # Number of bytes of host memory used
-host_seconds 417.62 # Real time elapsed on the host
-host_tick_rate 4551611662 # Simulator tick rate (ticks/s)
+host_inst_rate 160492 # Simulator instruction rate (inst/s)
+host_mem_usage 293848 # Number of bytes of host memory used
+host_seconds 355.10 # Real time elapsed on the host
+host_tick_rate 5352987788 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 56990237 # Number of instructions simulated
-sim_seconds 1.900844 # Number of seconds simulated
-sim_ticks 1900844230500 # Number of ticks simulated
+sim_insts 56990213 # Number of instructions simulated
+sim_seconds 1.900832 # Number of seconds simulated
+sim_ticks 1900831708500 # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits 5873671 # Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups 11166529 # Number of BTB lookups
-system.cpu0.BPredUnit.RASInCorrect 27790 # Number of incorrect RAS predictions.
-system.cpu0.BPredUnit.condIncorrect 685267 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted 10432996 # Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups 12491450 # Number of BP lookups
-system.cpu0.BPredUnit.usedRAS 879904 # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches 7524834 # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events 923111 # number cycles where commit BW limit reached
+system.cpu0.BPredUnit.BTBHits 5880494 # Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups 11174244 # Number of BTB lookups
+system.cpu0.BPredUnit.RASInCorrect 27800 # Number of incorrect RAS predictions.
+system.cpu0.BPredUnit.condIncorrect 685606 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted 10433425 # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups 12492393 # Number of BP lookups
+system.cpu0.BPredUnit.usedRAS 880061 # Number of times the RAS was used to get a target.
+system.cpu0.commit.COM:branches 7524876 # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events 920219 # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples 78256773 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean 0.636207 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev 1.403151 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples 78262011 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean 0.636166 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev 1.402915 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0 56995845 72.83% 72.83% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1 9310416 11.90% 84.73% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2 5430205 6.94% 91.67% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3 2440245 3.12% 94.79% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4 1860572 2.38% 97.16% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5 630930 0.81% 97.97% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6 344016 0.44% 98.41% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7 321433 0.41% 98.82% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8 923111 1.18% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0 56998112 72.83% 72.83% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1 9312532 11.90% 84.73% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2 5431102 6.94% 91.67% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3 2441098 3.12% 94.79% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4 1859715 2.38% 97.16% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5 630504 0.81% 97.97% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::6 344653 0.44% 98.41% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::7 324076 0.41% 98.82% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8 920219 1.18% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total 78256773 # Number of insts commited each cycle
-system.cpu0.commit.COM:count 49787514 # Number of instructions committed
-system.cpu0.commit.COM:loads 7895784 # Number of loads committed
+system.cpu0.commit.COM:committed_per_cycle::total 78262011 # Number of insts commited each cycle
+system.cpu0.commit.COM:count 49787612 # Number of instructions committed
+system.cpu0.commit.COM:loads 7895841 # Number of loads committed
system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed
-system.cpu0.commit.COM:refs 13320151 # Number of memory references committed
+system.cpu0.commit.COM:refs 13320204 # Number of memory references committed
system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts 652659 # The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts 49787514 # The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls 564772 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts 7271893 # The number of squashed insts skipped by commit
-system.cpu0.committedInsts 46926700 # Number of Instructions Simulated
-system.cpu0.committedInsts_total 46926700 # Number of Instructions Simulated
-system.cpu0.cpi 2.403270 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.403270 # CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses::0 178277 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 178277 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14385.010585 # average LoadLockedReq miss latency
+system.cpu0.commit.branchMispredicts 652972 # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts 49787612 # The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls 564765 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts 7275284 # The number of squashed insts skipped by commit
+system.cpu0.committedInsts 46926792 # Number of Instructions Simulated
+system.cpu0.committedInsts_total 46926792 # Number of Instructions Simulated
+system.cpu0.cpi 2.403365 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.403365 # CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses::0 178266 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 178266 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.082008 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10557.129525 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0 158910 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 158910 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 278594500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108634 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0 19367 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 19367 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10555.240699 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0 158902 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 158902 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 278514000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108624 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0 19364 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 19364 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_hits 4366 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158367500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084144 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158307500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084133 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 15001 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0 8018710 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8018710 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 23752.163525 # average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses 14998 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0 8019167 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8019167 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.581419 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.972926 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23767.536326 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0 6640866 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 6640866 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 32726776000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0 0.171829 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0 1377844 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1377844 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits 392731 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency 23413154000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122852 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0 6641537 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6641537 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 32725024000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0 0.171792 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0 1377630 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1377630 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits 392532 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency 23413352500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122843 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 985113 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920830500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13300.547196 # average StoreCondReq miss latency
+system.cpu0.dcache.ReadReq_mshr_misses 985098 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920862000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses::0 185115 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 185115 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13269.357045 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10297.264022 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits::0 181459 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 181459 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 48613500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019745 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10269.978106 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits::0 181460 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 181460 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 48499500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019744 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses::0 3655 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 3655 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37636500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019745 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37526500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019739 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses 3655 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses::0 5224193 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5224193 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 32390.296487 # average WriteReq miss latency
+system.cpu0.dcache.StoreCondReq_mshr_misses 3654 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses::0 5224194 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5224194 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 32391.467747 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30580.318877 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30578.461362 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0 3607335 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3607335 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 52370509997 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0 0.309494 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0 1616858 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1616858 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits 1353465 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency 8054641930 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050418 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_hits::0 3607293 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3607293 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 52373796592 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate::0 0.309502 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0 1616901 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1616901 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits 1353492 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency 8054641929 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050421 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 263393 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320665498 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8775.921635 # average number of cycles each access was blocked
+system.cpu0.dcache.WriteReq_mshr_misses 263409 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320645998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8778.099961 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 8.499931 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 83634 # number of cycles access was blocked
+system.cpu0.dcache.avg_refs 8.500462 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs 83583 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 733965430 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs 733699929 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0 13242903 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::0 13243361 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 13242903 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 28415.944557 # average overall miss latency
+system.cpu0.dcache.demand_accesses::total 13243361 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 28418.079690 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 25204.360996 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0 10248201 # number of demand (read+write) hits
+system.cpu0.dcache.demand_avg_mshr_miss_latency 25204.499798 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits::0 10248830 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 10248201 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 85097285997 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0 0.226136 # miss rate for demand accesses
+system.cpu0.dcache.demand_hits::total 10248830 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 85098820592 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate::0 0.226116 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0 2994702 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0 2994531 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2994702 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 1746196 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 31467795930 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0 0.094277 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_misses::total 2994531 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 1746024 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 31467994429 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate::0 0.094274 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 1248506 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses 1248507 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0 0.973616 # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 498.491480 # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::0 498.491430 # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses::0 13242903 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::0 13243361 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 13242903 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::0 28415.944557 # average overall miss latency
+system.cpu0.dcache.overall_accesses::total 13243361 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency::0 28418.079690 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 25204.360996 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 25204.499798 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0 10248201 # number of overall hits
+system.cpu0.dcache.overall_hits::0 10248830 # number of overall hits
system.cpu0.dcache.overall_hits::1 0 # number of overall hits
-system.cpu0.dcache.overall_hits::total 10248201 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 85097285997 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0 0.226136 # miss rate for overall accesses
+system.cpu0.dcache.overall_hits::total 10248830 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 85098820592 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate::0 0.226116 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0 2994702 # number of overall misses
+system.cpu0.dcache.overall_misses::0 2994531 # number of overall misses
system.cpu0.dcache.overall_misses::1 0 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2994702 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 1746196 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 31467795930 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::0 0.094277 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_misses::total 2994531 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 1746024 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 31467994429 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate::0 0.094274 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 1248506 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 2241495998 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_misses 1248507 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 2241507998 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements 1246705 # number of replacements
-system.cpu0.dcache.sampled_refs 1247217 # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements 1246700 # number of replacements
+system.cpu0.dcache.sampled_refs 1247212 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 497.491481 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 10601259 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 497.491430 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 10601878 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 721554 # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles 33796856 # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:BranchMispred 33338 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DECODE:BranchResolved 520908 # Number of times decode resolved a branch
-system.cpu0.decode.DECODE:DecodedInsts 62600964 # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles 32174872 # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles 11303760 # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles 1270160 # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:SquashedInsts 100637 # Number of squashed instructions handled by decode
-system.cpu0.decode.DECODE:UnblockCycles 981284 # Number of cycles decode is unblocking
-system.cpu0.dtb.data_accesses 794683 # DTB accesses
-system.cpu0.dtb.data_acv 699 # DTB access violations
-system.cpu0.dtb.data_hits 14241389 # DTB hits
-system.cpu0.dtb.data_misses 32519 # DTB misses
+system.cpu0.decode.DECODE:BlockedCycles 33792520 # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:BranchMispred 33358 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DECODE:BranchResolved 521061 # Number of times decode resolved a branch
+system.cpu0.decode.DECODE:DecodedInsts 62605463 # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles 32178672 # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles 11309201 # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles 1270716 # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:SquashedInsts 100684 # Number of squashed instructions handled by decode
+system.cpu0.decode.DECODE:UnblockCycles 981617 # Number of cycles decode is unblocking
+system.cpu0.dtb.data_accesses 795304 # DTB accesses
+system.cpu0.dtb.data_acv 690 # DTB access violations
+system.cpu0.dtb.data_hits 14242761 # DTB hits
+system.cpu0.dtb.data_misses 32467 # DTB misses
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.read_accesses 599310 # DTB read accesses
-system.cpu0.dtb.read_acv 523 # DTB read access violations
-system.cpu0.dtb.read_hits 8657125 # DTB read hits
-system.cpu0.dtb.read_misses 26727 # DTB read misses
-system.cpu0.dtb.write_accesses 195373 # DTB write accesses
-system.cpu0.dtb.write_acv 176 # DTB write access violations
-system.cpu0.dtb.write_hits 5584264 # DTB write hits
-system.cpu0.dtb.write_misses 5792 # DTB write misses
-system.cpu0.fetch.Branches 12491450 # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines 7791215 # Number of cache lines fetched
-system.cpu0.fetch.Cycles 20268333 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes 374565 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts 63688508 # Number of instructions fetch has processed
-system.cpu0.fetch.MiscStallCycles 1103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.SquashCycles 745343 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate 0.110762 # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles 7791215 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.predictedBranches 6753575 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate 0.564727 # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist::samples 79526933 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.800842 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.104211 # Number of instructions fetched each cycle (Total)
+system.cpu0.dtb.read_accesses 599691 # DTB read accesses
+system.cpu0.dtb.read_acv 517 # DTB read access violations
+system.cpu0.dtb.read_hits 8658240 # DTB read hits
+system.cpu0.dtb.read_misses 26670 # DTB read misses
+system.cpu0.dtb.write_accesses 195613 # DTB write accesses
+system.cpu0.dtb.write_acv 173 # DTB write access violations
+system.cpu0.dtb.write_hits 5584521 # DTB write hits
+system.cpu0.dtb.write_misses 5797 # DTB write misses
+system.cpu0.fetch.Branches 12492393 # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines 7792591 # Number of cache lines fetched
+system.cpu0.fetch.Cycles 20275777 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes 374501 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts 63694095 # Number of instructions fetch has processed
+system.cpu0.fetch.MiscStallCycles 1162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.SquashCycles 745780 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate 0.110766 # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles 7792591 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches 6760555 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate 0.564753 # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::samples 79532727 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.800854 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.104099 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 67079407 84.35% 84.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 896436 1.13% 85.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1772079 2.23% 87.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 811632 1.02% 88.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2745328 3.45% 92.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 585266 0.74% 92.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 679619 0.85% 93.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 829666 1.04% 94.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4127500 5.19% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 67079150 84.34% 84.34% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 900735 1.13% 85.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1776168 2.23% 87.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 808150 1.02% 88.72% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2746406 3.45% 92.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 585611 0.74% 92.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 679507 0.85% 93.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 830147 1.04% 94.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4126853 5.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 79526933 # Number of instructions fetched each cycle (Total)
-system.cpu0.icache.ReadReq_accesses::0 7791215 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 7791215 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency::0 15067.927393 # average ReadReq miss latency
+system.cpu0.fetch.rateDist::total 79532727 # Number of instructions fetched each cycle (Total)
+system.cpu0.icache.ReadReq_accesses::0 7792591 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 7792591 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency::0 15067.531748 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.913224 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits::0 6933667 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6933667 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_miss_rate::0 0.110066 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::0 857548 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 857548 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits 36674 # number of ReadReq MSHR hits
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system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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-system.cpu0.icache.blocked::no_mshrs 51 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses::0 7791215 # number of demand (read+write) accesses
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system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
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-system.cpu0.icache.demand_hits::0 6933667 # number of demand (read+write) hits
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system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6933667 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 12921471000 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 857548 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 36674 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 9865192500 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 820874 # number of demand (read+write) MSHR misses
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0 509.861243 # Average occupied blocks per context
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system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
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-system.cpu0.icache.overall_avg_miss_latency::0 15067.927393 # average overall miss latency
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system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 12017.913224 # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::0 6933667 # number of overall hits
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system.cpu0.icache.overall_hits::1 0 # number of overall hits
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system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu0.icache.overall_misses::1 0 # number of overall misses
-system.cpu0.icache.overall_misses::total 857548 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 36674 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 9865192500 # number of overall MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 820874 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements 820245 # number of replacements
-system.cpu0.icache.sampled_refs 820756 # Sample count of references to valid blocks.
+system.cpu0.icache.replacements 820241 # number of replacements
+system.cpu0.icache.sampled_refs 820752 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 509.861243 # Cycle average of tags in use
-system.cpu0.icache.total_refs 6933667 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 509.861229 # Cycle average of tags in use
+system.cpu0.icache.total_refs 6935061 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 109 # number of writebacks
-system.cpu0.idleCycles 33250612 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches 8091553 # Number of branches executed
-system.cpu0.iew.EXEC:nop 3189610 # number of nop insts executed
+system.cpu0.idleCycles 33249487 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.iew.EXEC:branches 8091689 # Number of branches executed
+system.cpu0.iew.EXEC:nop 3189515 # number of nop insts executed
system.cpu0.iew.EXEC:rate 0.446670 # Inst execution rate
-system.cpu0.iew.EXEC:refs 14308443 # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores 5602810 # Number of stores executed
+system.cpu0.iew.EXEC:refs 14309755 # number of memory reference insts executed
+system.cpu0.iew.EXEC:stores 5603066 # Number of stores executed
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu0.iew.WB:consumers 31619553 # num instructions consuming a value
-system.cpu0.iew.WB:count 49998381 # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout 0.757763 # average fanout of values written-back
+system.cpu0.iew.WB:consumers 31608779 # num instructions consuming a value
+system.cpu0.iew.WB:count 49999865 # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout 0.758055 # average fanout of values written-back
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers 23960113 # num instructions producing a value
-system.cpu0.iew.WB:rate 0.443336 # insts written-back per cycle
-system.cpu0.iew.WB:sent 50080785 # cumulative count of insts sent to commit
-system.cpu0.iew.branchMispredicts 711622 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewBlockCycles 9015836 # Number of cycles IEW is blocking
-system.cpu0.iew.iewDispLoadInsts 9134167 # Number of dispatched load instructions
-system.cpu0.iew.iewDispNonSpecInsts 1511990 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewDispSquashedInsts 755493 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispStoreInsts 5841972 # Number of dispatched store instructions
-system.cpu0.iew.iewDispatchedInsts 57170075 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewExecLoadInsts 8705633 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 463276 # Number of squashed instructions skipped in execute
-system.cpu0.iew.iewExecutedInsts 50374391 # Number of executed instructions
-system.cpu0.iew.iewIQFullEvents 59438 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.WB:producers 23961182 # num instructions producing a value
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+system.cpu0.iew.WB:sent 50082132 # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts 711844 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles 9016513 # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts 9135520 # Number of dispatched load instructions
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+system.cpu0.iew.iewDispSquashedInsts 755935 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts 5842466 # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts 57173513 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewExecLoadInsts 8706689 # Number of load instructions executed
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+system.cpu0.iew.iewExecutedInsts 50376392 # Number of executed instructions
+system.cpu0.iew.iewIQFullEvents 59411 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewLSQFullEvents 6976 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.iewSquashCycles 1270160 # Number of cycles IEW is squashing
-system.cpu0.iew.iewUnblockCycles 547257 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewLSQFullEvents 6975 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles 1270716 # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles 547260 # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread.0.cacheBlocked 121631 # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.lsq.thread.0.forwLoads 411302 # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread.0.ignoredResponses 10774 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.cacheBlocked 122212 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads 411295 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses 10786 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread.0.memOrderViolation 38966 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread.0.rescheduledLoads 18610 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread.0.squashedLoads 1238383 # Number of loads squashed
-system.cpu0.iew.lsq.thread.0.squashedStores 417605 # Number of stores squashed
-system.cpu0.iew.memOrderViolationEvents 38966 # Number of memory order violations
-system.cpu0.iew.predictedNotTakenIncorrect 331944 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.predictedTakenIncorrect 379678 # Number of branches that were predicted taken incorrectly
-system.cpu0.ipc 0.416100 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.416100 # IPC: Total IPC of All Threads
+system.cpu0.iew.lsq.thread.0.memOrderViolation 39006 # Number of memory ordering violations
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+system.cpu0.iew.memOrderViolationEvents 39006 # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect 331745 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect 380099 # Number of branches that were predicted taken incorrectly
+system.cpu0.ipc 0.416083 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.416083 # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35331602 69.50% 69.51% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntMult 55961 0.11% 69.62% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.62% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.65% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.65% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.65% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.65% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35332190 69.50% 69.50% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntMult 55947 0.11% 69.61% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.61% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.64% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.64% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.64% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.64% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemRead 9004352 17.71% 87.36% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645593 11.11% 98.47% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779196 1.53% 100.00% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemRead 9005421 17.71% 87.36% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645944 11.11% 98.47% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779180 1.53% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::total 50837669 # Type of FU issued
-system.cpu0.iq.ISSUE:fu_busy_cnt 379948 # FU busy when requested
-system.cpu0.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.ISSUE:FU_type_0::total 50839647 # Type of FU issued
+system.cpu0.iq.ISSUE:fu_busy_cnt 380083 # FU busy when requested
+system.cpu0.iq.ISSUE:fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntAlu 41291 10.87% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.87% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead 225058 59.23% 70.10% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite 113599 29.90% 100.00% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntAlu 41221 10.85% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.85% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemRead 225189 59.25% 70.09% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemWrite 113673 29.91% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples 79526933 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639251 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.210486 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::samples 79532727 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639229 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.210023 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0 54768546 68.87% 68.87% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1 12090793 15.20% 84.07% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2 5440746 6.84% 90.91% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3 3421929 4.30% 95.22% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4 2219727 2.79% 98.01% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5 991235 1.25% 99.25% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6 436578 0.55% 99.80% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::7 113986 0.14% 99.95% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::8 43393 0.05% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::0 54768244 68.86% 68.86% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::1 12092577 15.20% 84.07% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::2 5445890 6.85% 90.91% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::3 3420529 4.30% 95.22% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::4 2219923 2.79% 98.01% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::5 995680 1.25% 99.26% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::6 437086 0.55% 99.81% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::7 109289 0.14% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::8 43509 0.05% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total 79526933 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate 0.450778 # Inst issue rate
-system.cpu0.iq.iqInstsAdded 52258300 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqInstsIssued 50837669 # Number of instructions issued
-system.cpu0.iq.iqNonSpecInstsAdded 1722165 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined 6733244 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedInstsIssued 24149 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedNonSpecRemoved 1157393 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.iqSquashedOperandsExamined 3421850 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.ISSUE:issued_per_cycle::total 79532727 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:rate 0.450777 # Inst issue rate
+system.cpu0.iq.iqInstsAdded 52261894 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued 50839647 # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded 1722104 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined 6736109 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued 24176 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved 1157339 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined 3425002 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.fetch_accesses 951504 # ITB accesses
-system.cpu0.itb.fetch_acv 721 # ITB acv
-system.cpu0.itb.fetch_hits 922631 # ITB hits
-system.cpu0.itb.fetch_misses 28873 # ITB misses
+system.cpu0.itb.fetch_accesses 951977 # ITB accesses
+system.cpu0.itb.fetch_acv 722 # ITB acv
+system.cpu0.itb.fetch_hits 923088 # ITB hits
+system.cpu0.itb.fetch_misses 28889 # ITB misses
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed
system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 147045 90.75% 93.03% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 147043 90.75% 93.03% # number of callpals executed
system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed
system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed
system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 162037 # number of callpals executed
+system.cpu0.kern.callpal::total 162035 # number of callpals executed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 176107 # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei 176106 # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce 6625 # number of quiesce instructions executed
system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 89359 58.06% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 153913 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 89357 58.06% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 153911 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1862714429000 97.99% 97.99% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 96239500 0.01% 98.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 398463500 0.02% 98.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 103371000 0.01% 98.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 37530876000 1.97% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1900843379000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0 1862701571500 97.99% 97.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 96288500 0.01% 98.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 398425500 0.02% 98.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 103369500 0.01% 98.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 37531203000 1.97% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1900830858000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.682785 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good::kernel 1172
-system.cpu0.kern.mode_good::user 1173
+system.cpu0.kern.ipl_used::31 0.682800 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good::kernel 1170
+system.cpu0.kern.mode_good::user 1171
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1171 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel 0.170052 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.169762 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1898870092500 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1973278500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel 1898856944500 99.90% 99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 1973905500 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3288 # number of times the context was actually changed
system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed
system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed
system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 201 # number of syscalls executed
-system.cpu0.memDep0.conflictingLoads 2303690 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1915346 # Number of conflicting stores.
-system.cpu0.memDep0.insertedLoads 9134167 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5841972 # Number of stores inserted to the mem dependence unit.
-system.cpu0.numCycles 112777545 # number of cpu cycles simulated
-system.cpu0.rename.RENAME:BlockCycles 12780906 # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps 33989447 # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IQFullEvents 1008250 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles 33579404 # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents 1370622 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:ROBFullEvents 43227 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.RENAME:RenameLookups 72557706 # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts 59333926 # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands 39987201 # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles 11036329 # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles 1270160 # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles 3988199 # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps 5997752 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:serializeStallCycles 16871933 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts 1393572 # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts 10085816 # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts 207581 # count of temporary serializing insts renamed
-system.cpu0.timesIdled 1187611 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.memDep0.conflictingLoads 2309039 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1917455 # Number of conflicting stores.
+system.cpu0.memDep0.insertedLoads 9135520 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5842466 # Number of stores inserted to the mem dependence unit.
+system.cpu0.numCycles 112782214 # number of cpu cycles simulated
+system.cpu0.rename.RENAME:BlockCycles 12781389 # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps 33989509 # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IQFullEvents 1007909 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.RENAME:IdleCycles 33583011 # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents 1370380 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:ROBFullEvents 43256 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.RENAME:RenameLookups 72564759 # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts 59338809 # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands 39990302 # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles 11042113 # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles 1270716 # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles 3987723 # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps 6000791 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:serializeStallCycles 16867773 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts 1393581 # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts 10085074 # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts 207606 # count of temporary serializing insts renamed
+system.cpu0.timesIdled 1187595 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.BTBHits 1157962 # Number of BTB hits
-system.cpu1.BPredUnit.BTBLookups 2699963 # Number of BTB lookups
-system.cpu1.BPredUnit.RASInCorrect 8335 # Number of incorrect RAS predictions.
-system.cpu1.BPredUnit.condIncorrect 172116 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.condPredicted 2481640 # Number of conditional branches predicted
-system.cpu1.BPredUnit.lookups 2995076 # Number of BP lookups
-system.cpu1.BPredUnit.usedRAS 209806 # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches 1517916 # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events 197525 # number cycles where commit BW limit reached
+system.cpu1.BPredUnit.BTBHits 1159628 # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups 2701076 # Number of BTB lookups
+system.cpu1.BPredUnit.RASInCorrect 8300 # Number of incorrect RAS predictions.
+system.cpu1.BPredUnit.condIncorrect 172219 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.condPredicted 2481214 # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups 2994712 # Number of BP lookups
+system.cpu1.BPredUnit.usedRAS 209821 # Number of times the RAS was used to get a target.
+system.cpu1.commit.COM:branches 1517871 # Number of branches committed
+system.cpu1.commit.COM:bw_lim_events 197774 # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples 17848598 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean 0.593368 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev 1.404700 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::samples 17831958 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::mean 0.593915 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::stdev 1.406567 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0 13459755 75.41% 75.41% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1 2076221 11.63% 87.04% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2 798391 4.47% 91.52% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3 569134 3.19% 94.70% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4 394612 2.21% 96.92% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5 153567 0.86% 97.78% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::6 111850 0.63% 98.40% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::7 87543 0.49% 98.89% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::8 197525 1.11% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::0 13448737 75.42% 75.42% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::1 2070572 11.61% 87.03% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::2 799926 4.49% 91.52% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::3 567078 3.18% 94.70% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::4 394341 2.21% 96.91% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::5 151842 0.85% 97.76% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::6 111575 0.63% 98.39% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::7 90113 0.51% 98.89% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::8 197774 1.11% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total 17848598 # Number of insts commited each cycle
-system.cpu1.commit.COM:count 10590789 # Number of instructions committed
-system.cpu1.commit.COM:loads 1991065 # Number of loads committed
+system.cpu1.commit.COM:committed_per_cycle::total 17831958 # Number of insts commited each cycle
+system.cpu1.commit.COM:count 10590665 # Number of instructions committed
+system.cpu1.commit.COM:loads 1991024 # Number of loads committed
system.cpu1.commit.COM:membars 52740 # Number of memory barriers committed
-system.cpu1.commit.COM:refs 3374997 # Number of memory references committed
+system.cpu1.commit.COM:refs 3374947 # Number of memory references committed
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.branchMispredicts 164251 # The number of times a branch was mispredicted
-system.cpu1.commit.commitCommittedInsts 10590789 # The number of committed instructions
-system.cpu1.commit.commitNonSpecStalls 163017 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.commitSquashedInsts 1716683 # The number of squashed insts skipped by commit
-system.cpu1.committedInsts 10063537 # Number of Instructions Simulated
-system.cpu1.committedInsts_total 10063537 # Number of Instructions Simulated
-system.cpu1.cpi 1.953144 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.953144 # CPI: Total CPI of All Threads
-system.cpu1.dcache.LoadLockedReq_accesses::0 46385 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 46385 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11093.156176 # average LoadLockedReq miss latency
+system.cpu1.commit.branchMispredicts 164356 # The number of times a branch was mispredicted
+system.cpu1.commit.commitCommittedInsts 10590665 # The number of committed instructions
+system.cpu1.commit.commitNonSpecStalls 163015 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.commitSquashedInsts 1719784 # The number of squashed insts skipped by commit
+system.cpu1.committedInsts 10063421 # Number of Instructions Simulated
+system.cpu1.committedInsts_total 10063421 # Number of Instructions Simulated
+system.cpu1.cpi 1.950737 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.950737 # CPI: Total CPI of All Threads
+system.cpu1.dcache.LoadLockedReq_accesses::0 46382 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 46382 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11099.301842 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8017.085427 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::0 39649 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 39649 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency 74723500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145219 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0 6736 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 6736 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_hits 766 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47862000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128705 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8021.283727 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits::0 39650 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 39650 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency 74720500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145143 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses::0 6732 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 6732 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_hits 765 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47863000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128649 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 5970 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::0 2063183 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 2063183 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 15106.279717 # average ReadReq miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_misses 5967 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses::0 2063263 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 2063263 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 15045.752696 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11684.123629 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11684.073615 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::0 1870531 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 1870531 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 2910255000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::0 0.093376 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0 192652 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 192652 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_hits 97561 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency 1111055000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046089 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_hits::0 1869340 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 1869340 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 2917717500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate::0 0.093989 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses::0 193923 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 193923 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_hits 98779 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_miss_latency 1111669500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046113 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 95091 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses::0 43197 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 43197 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13112.263417 # average StoreCondReq miss latency
+system.cpu1.dcache.ReadReq_mshr_misses 95144 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses::0 43195 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 43195 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13108.977686 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10114.107884 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::0 39340 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 39340 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency 50574000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089289 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0 3857 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 3857 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39000000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089265 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10107.291126 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits::0 39341 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 39341 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency 50522000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089223 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0 3854 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 3854 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 38953500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089223 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses 3856 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses::0 1334344 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 1334344 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 21202.003457 # average WriteReq miss latency
+system.cpu1.dcache.StoreCondReq_mshr_misses 3854 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses::0 1334339 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 1334339 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 21230.266809 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18758.167110 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18781.127505 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::0 1085015 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 1085015 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 5286274320 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::0 0.186855 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0 249329 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 249329 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_hits 200876 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_miss_latency 908889471 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_hits::0 1084932 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 1084932 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 5294977154 # number of WriteReq miss cycles
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+system.cpu1.dcache.WriteReq_misses::0 249407 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 249407 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_hits 200954 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_miss_latency 910001971 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036312 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses 48453 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377675000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10123.559438 # average number of cycles each access was blocked
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377711000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9964.987699 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 22.895667 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs 5123 # number of cycles access was blocked
+system.cpu1.dcache.avg_refs 22.877704 # Average number of references to valid blocks.
+system.cpu1.dcache.blocked::no_mshrs 5284 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs 51862995 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_mshrs 52654995 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0 3397527 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::0 3397602 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 3397527 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 18544.981164 # average overall miss latency
+system.cpu1.dcache.demand_accesses::total 3397602 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 18525.014445 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 14071.953345 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0 2955546 # number of demand (read+write) hits
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+system.cpu1.dcache.demand_hits::0 2954272 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 2955546 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 8196529320 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0 0.130089 # miss rate for demand accesses
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+system.cpu1.dcache.demand_miss_latency 8212694654 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate::0 0.130483 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 441981 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 298437 # number of demand (read+write) MSHR hits
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-system.cpu1.dcache.demand_mshr_miss_rate::0 0.042250 # mshr miss rate for demand accesses
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system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 143544 # number of demand (read+write) MSHR misses
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.933247 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0 477.822541 # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses::0 3397527 # number of overall (read+write) accesses
+system.cpu1.dcache.occ_%::0 0.933246 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0 477.822051 # Average occupied blocks per context
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system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 3397527 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::0 18544.981164 # average overall miss latency
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system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 14071.953345 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 14078.786263 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0 2955546 # number of overall hits
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system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 2955546 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 8196529320 # number of overall miss cycles
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system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0 441981 # number of overall misses
+system.cpu1.dcache.overall_misses::0 443330 # number of overall misses
system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 441981 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 298437 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 2019944471 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::0 0.042250 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_misses::total 443330 # number of overall misses
+system.cpu1.dcache.overall_mshr_hits 299733 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency 2021671471 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate::0 0.042264 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 143544 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 395352000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_misses 143597 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 395388500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements 132498 # number of replacements
-system.cpu1.dcache.sampled_refs 132892 # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements 132546 # number of replacements
+system.cpu1.dcache.sampled_refs 132940 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 477.822541 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 3042651 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1877659701000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tagsinuse 477.822051 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 3041362 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1877659740000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 88702 # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles 6987029 # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:BlockedCycles 6966662 # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BranchMispred 7945 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DECODE:BranchResolved 127739 # Number of times decode resolved a branch
-system.cpu1.decode.DECODE:DecodedInsts 13932578 # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles 8260937 # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles 2501859 # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles 305063 # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:SquashedInsts 23694 # Number of squashed instructions handled by decode
-system.cpu1.decode.DECODE:UnblockCycles 98772 # Number of cycles decode is unblocking
-system.cpu1.dtb.data_accesses 453342 # DTB accesses
+system.cpu1.decode.DECODE:BranchResolved 127784 # Number of times decode resolved a branch
+system.cpu1.decode.DECODE:DecodedInsts 13937245 # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles 8263002 # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles 2503476 # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles 305841 # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:SquashedInsts 23696 # Number of squashed instructions handled by decode
+system.cpu1.decode.DECODE:UnblockCycles 98817 # Number of cycles decode is unblocking
+system.cpu1.dtb.data_accesses 453673 # DTB accesses
system.cpu1.dtb.data_acv 183 # DTB access violations
-system.cpu1.dtb.data_hits 3613400 # DTB hits
-system.cpu1.dtb.data_misses 12964 # DTB misses
+system.cpu1.dtb.data_hits 3613751 # DTB hits
+system.cpu1.dtb.data_misses 13007 # DTB misses
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.read_accesses 321975 # DTB read accesses
-system.cpu1.dtb.read_acv 83 # DTB read access violations
-system.cpu1.dtb.read_hits 2187186 # DTB read hits
-system.cpu1.dtb.read_misses 10487 # DTB read misses
-system.cpu1.dtb.write_accesses 131367 # DTB write accesses
-system.cpu1.dtb.write_acv 100 # DTB write access violations
-system.cpu1.dtb.write_hits 1426214 # DTB write hits
-system.cpu1.dtb.write_misses 2477 # DTB write misses
-system.cpu1.fetch.Branches 2995076 # Number of branches that fetch encountered
-system.cpu1.fetch.CacheLines 1674453 # Number of cache lines fetched
-system.cpu1.fetch.Cycles 4316686 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.IcacheSquashes 103652 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.Insts 14184875 # Number of instructions fetch has processed
-system.cpu1.fetch.MiscStallCycles 463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.SquashCycles 191233 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate 0.152378 # Number of branch fetches per cycle
-system.cpu1.fetch.icacheStallCycles 1674453 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.predictedBranches 1367768 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate 0.721673 # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist::samples 18153661 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.781378 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.130034 # Number of instructions fetched each cycle (Total)
+system.cpu1.dtb.read_accesses 322326 # DTB read accesses
+system.cpu1.dtb.read_acv 82 # DTB read access violations
+system.cpu1.dtb.read_hits 2187602 # DTB read hits
+system.cpu1.dtb.read_misses 10512 # DTB read misses
+system.cpu1.dtb.write_accesses 131347 # DTB write accesses
+system.cpu1.dtb.write_acv 101 # DTB write access violations
+system.cpu1.dtb.write_hits 1426149 # DTB write hits
+system.cpu1.dtb.write_misses 2495 # DTB write misses
+system.cpu1.fetch.Branches 2994712 # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines 1675694 # Number of cache lines fetched
+system.cpu1.fetch.Cycles 4319661 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes 103833 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts 14189706 # Number of instructions fetch has processed
+system.cpu1.fetch.MiscStallCycles 562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.SquashCycles 191595 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate 0.152550 # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles 1675694 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches 1369449 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate 0.722818 # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::samples 18137799 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.782328 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.130924 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 15520231 85.49% 85.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 211004 1.16% 86.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 323759 1.78% 88.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 198428 1.09% 89.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 375870 2.07% 91.60% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 125712 0.69% 92.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 169249 0.93% 93.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 251729 1.39% 94.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 977679 5.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 15502694 85.47% 85.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 211332 1.17% 86.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 324186 1.79% 88.42% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 198526 1.09% 89.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 376340 2.07% 91.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 125878 0.69% 92.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 169328 0.93% 93.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 252414 1.39% 94.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 977101 5.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 18153661 # Number of instructions fetched each cycle (Total)
-system.cpu1.icache.ReadReq_accesses::0 1674453 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 1674453 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14671.340426 # average ReadReq miss latency
+system.cpu1.fetch.rateDist::total 18137799 # Number of instructions fetched each cycle (Total)
+system.cpu1.icache.ReadReq_accesses::0 1675694 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 1675694 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14669.843213 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.734234 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits::0 1410604 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 1410604 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 3871018500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate::0 0.157573 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::0 263849 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 263849 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_hits 8241 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_miss_latency 2972397500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152652 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.039136 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits::0 1411833 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 1411833 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency 3870799500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate::0 0.157464 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses::0 263861 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 263861 # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_hits 8268 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_miss_latency 2972301000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152530 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 255608 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses 255593 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs 4444.444444 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 5.519875 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 5.524987 # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs 40000 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses::0 1674453 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::0 1675694 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 1674453 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency::0 14671.340426 # average overall miss latency
+system.cpu1.icache.demand_accesses::total 1675694 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency::0 14669.843213 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11628.734234 # average overall mshr miss latency
-system.cpu1.icache.demand_hits::0 1410604 # number of demand (read+write) hits
+system.cpu1.icache.demand_avg_mshr_miss_latency 11629.039136 # average overall mshr miss latency
+system.cpu1.icache.demand_hits::0 1411833 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 1410604 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 3871018500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate::0 0.157573 # miss rate for demand accesses
+system.cpu1.icache.demand_hits::total 1411833 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 3870799500 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate::0 0.157464 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.icache.demand_misses::0 263849 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::0 263861 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 263849 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 8241 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 2972397500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::0 0.152652 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_misses::total 263861 # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits 8268 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency 2972301000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate::0 0.152530 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 255608 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses 255593 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0 0.900435 # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0 461.022947 # Average occupied blocks per context
-system.cpu1.icache.overall_accesses::0 1674453 # number of overall (read+write) accesses
+system.cpu1.icache.occ_blocks::0 461.022612 # Average occupied blocks per context
+system.cpu1.icache.overall_accesses::0 1675694 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 1674453 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::0 14671.340426 # average overall miss latency
+system.cpu1.icache.overall_accesses::total 1675694 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency::0 14669.843213 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11628.734234 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11629.039136 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::0 1410604 # number of overall hits
+system.cpu1.icache.overall_hits::0 1411833 # number of overall hits
system.cpu1.icache.overall_hits::1 0 # number of overall hits
-system.cpu1.icache.overall_hits::total 1410604 # number of overall hits
-system.cpu1.icache.overall_miss_latency 3871018500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate::0 0.157573 # miss rate for overall accesses
+system.cpu1.icache.overall_hits::total 1411833 # number of overall hits
+system.cpu1.icache.overall_miss_latency 3870799500 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate::0 0.157464 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.overall_misses::0 263849 # number of overall misses
+system.cpu1.icache.overall_misses::0 263861 # number of overall misses
system.cpu1.icache.overall_misses::1 0 # number of overall misses
-system.cpu1.icache.overall_misses::total 263849 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 8241 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 2972397500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate::0 0.152652 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_misses::total 263861 # number of overall misses
+system.cpu1.icache.overall_mshr_hits 8268 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency 2972301000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate::0 0.152530 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 255608 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses 255593 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements 255038 # number of replacements
-system.cpu1.icache.sampled_refs 255550 # Sample count of references to valid blocks.
+system.cpu1.icache.replacements 255024 # number of replacements
+system.cpu1.icache.sampled_refs 255536 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 461.022947 # Cycle average of tags in use
-system.cpu1.icache.total_refs 1410604 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1897916451000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tagsinuse 461.022612 # Cycle average of tags in use
+system.cpu1.icache.total_refs 1411833 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1897916222000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 13 # number of writebacks
-system.cpu1.idleCycles 1501880 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches 1627207 # Number of branches executed
-system.cpu1.iew.EXEC:nop 601288 # number of nop insts executed
-system.cpu1.iew.EXEC:rate 0.550852 # Inst execution rate
-system.cpu1.iew.EXEC:refs 3642900 # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores 1435734 # Number of stores executed
+system.cpu1.idleCycles 1493284 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches 1627599 # Number of branches executed
+system.cpu1.iew.EXEC:nop 601660 # number of nop insts executed
+system.cpu1.iew.EXEC:rate 0.551671 # Inst execution rate
+system.cpu1.iew.EXEC:refs 3643304 # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores 1435691 # Number of stores executed
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu1.iew.WB:consumers 6254497 # num instructions consuming a value
-system.cpu1.iew.WB:count 10719851 # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout 0.736543 # average fanout of values written-back
+system.cpu1.iew.WB:consumers 6256127 # num instructions consuming a value
+system.cpu1.iew.WB:count 10722196 # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout 0.736602 # average fanout of values written-back
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers 4606706 # num instructions producing a value
-system.cpu1.iew.WB:rate 0.545386 # insts written-back per cycle
-system.cpu1.iew.WB:sent 10743061 # cumulative count of insts sent to commit
-system.cpu1.iew.branchMispredicts 178420 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewBlockCycles 265381 # Number of cycles IEW is blocking
-system.cpu1.iew.iewDispLoadInsts 2308328 # Number of dispatched load instructions
-system.cpu1.iew.iewDispNonSpecInsts 500549 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewDispSquashedInsts 208852 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispStoreInsts 1509637 # Number of dispatched store instructions
-system.cpu1.iew.iewDispatchedInsts 12390699 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewExecLoadInsts 2207166 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 106974 # Number of squashed instructions skipped in execute
-system.cpu1.iew.iewExecutedInsts 10827293 # Number of executed instructions
-system.cpu1.iew.iewIQFullEvents 2483 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.WB:producers 4608274 # num instructions producing a value
+system.cpu1.iew.WB:rate 0.546185 # insts written-back per cycle
+system.cpu1.iew.WB:sent 10745464 # cumulative count of insts sent to commit
+system.cpu1.iew.branchMispredicts 178521 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewBlockCycles 256730 # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts 2308752 # Number of dispatched load instructions
+system.cpu1.iew.iewDispNonSpecInsts 500484 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewDispSquashedInsts 209358 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispStoreInsts 1509923 # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts 12393438 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts 2207613 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 106928 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts 10829897 # Number of executed instructions
+system.cpu1.iew.iewIQFullEvents 2615 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewLSQFullEvents 4852 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.iewSquashCycles 305063 # Number of cycles IEW is squashing
-system.cpu1.iew.iewUnblockCycles 10314 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewLSQFullEvents 4833 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 305841 # Number of cycles IEW is squashing
+system.cpu1.iew.iewUnblockCycles 10301 # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread.0.cacheBlocked 22342 # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.lsq.thread.0.forwLoads 67469 # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread.0.ignoredResponses 2212 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread.0.cacheBlocked 22559 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread.0.forwLoads 67759 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread.0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread.0.memOrderViolation 10592 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread.0.memOrderViolation 10819 # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads 380 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread.0.squashedLoads 317263 # Number of loads squashed
-system.cpu1.iew.lsq.thread.0.squashedStores 125705 # Number of stores squashed
-system.cpu1.iew.memOrderViolationEvents 10592 # Number of memory order violations
-system.cpu1.iew.predictedNotTakenIncorrect 104736 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.predictedTakenIncorrect 73684 # Number of branches that were predicted taken incorrectly
-system.cpu1.ipc 0.511995 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.511995 # IPC: Total IPC of All Threads
+system.cpu1.iew.lsq.thread.0.squashedLoads 317728 # Number of loads squashed
+system.cpu1.iew.lsq.thread.0.squashedStores 126000 # Number of stores squashed
+system.cpu1.iew.memOrderViolationEvents 10819 # Number of memory order violations
+system.cpu1.iew.predictedNotTakenIncorrect 104538 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.predictedTakenIncorrect 73983 # Number of branches that were predicted taken incorrectly
+system.cpu1.ipc 0.512627 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.512627 # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3525 0.03% 0.03% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6856403 62.71% 62.74% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult 17935 0.16% 62.90% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.90% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6858697 62.71% 62.74% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntMult 17938 0.16% 62.91% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.01% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.01% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.01% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.01% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282654 20.88% 83.90% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1452686 13.29% 97.18% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307870 2.82% 100.00% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.03% # Type of FU issued
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+system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282943 20.87% 83.90% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1452642 13.28% 97.18% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307886 2.82% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total 10934267 # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt 157620 # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate 0.014415 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:FU_type_0::total 10936825 # Type of FU issued
+system.cpu1.iq.ISSUE:fu_busy_cnt 157834 # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate 0.014431 # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu 4070 2.58% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.58% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead 93965 59.61% 62.20% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite 59585 37.80% 100.00% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntAlu 3969 2.51% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.51% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemRead 94191 59.68% 62.19% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemWrite 59674 37.81% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples 18153661 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.602317 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.206394 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::samples 18137799 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.602985 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.207807 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0 12924725 71.20% 71.20% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1 2574747 14.18% 85.38% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2 1068107 5.88% 91.26% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3 685428 3.78% 95.04% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4 525394 2.89% 97.93% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::5 238254 1.31% 99.25% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::6 93756 0.52% 99.76% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::7 34360 0.19% 99.95% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::8 8890 0.05% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::0 12914156 71.20% 71.20% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::1 2567061 14.15% 85.35% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::2 1068417 5.89% 91.24% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::3 686600 3.79% 95.03% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::4 525581 2.90% 97.93% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::5 238380 1.31% 99.24% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::6 93711 0.52% 99.76% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::7 34504 0.19% 99.95% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::8 9389 0.05% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total 18153661 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate 0.556294 # Inst issue rate
-system.cpu1.iq.iqInstsAdded 11233407 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqInstsIssued 10934267 # Number of instructions issued
-system.cpu1.iq.iqNonSpecInstsAdded 556004 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqSquashedInstsExamined 1651489 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedInstsIssued 10261 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedNonSpecRemoved 392987 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.iqSquashedOperandsExamined 847945 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.ISSUE:issued_per_cycle::total 18137799 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:rate 0.557118 # Inst issue rate
+system.cpu1.iq.iqInstsAdded 11235835 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued 10936825 # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded 555943 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined 1653815 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsIssued 10214 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedNonSpecRemoved 392928 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.iqSquashedOperandsExamined 848491 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.fetch_accesses 448239 # ITB accesses
-system.cpu1.itb.fetch_acv 291 # ITB acv
-system.cpu1.itb.fetch_hits 439727 # ITB hits
-system.cpu1.itb.fetch_misses 8512 # ITB misses
+system.cpu1.itb.fetch_accesses 449298 # ITB accesses
+system.cpu1.itb.fetch_acv 268 # ITB acv
+system.cpu1.itb.fetch_hits 440704 # ITB hits
+system.cpu1.itb.fetch_misses 8594 # ITB misses
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed
system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 49367 86.50% 89.53% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 49369 86.50% 89.53% # number of callpals executed
system.cpu1.kern.callpal::rdps 2383 4.18% 93.70% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed
system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed
system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 57069 # number of callpals executed
+system.cpu1.kern.callpal::total 57071 # number of callpals executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.hwrei 64908 # number of hwrei instructions executed
+system.cpu1.kern.inst.hwrei 64910 # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed
system.cpu1.kern.ipl_count::0 20666 37.58% 37.58% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1922 3.49% 41.07% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 32054 58.29% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 54993 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 32056 58.29% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 54995 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 20159 47.72% 47.72% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 19808 46.89% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 42240 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1870788653000 98.44% 98.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 347996000 0.02% 98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 137644000 0.01% 98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 29218866000 1.54% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1900493159000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0 1870775538500 98.44% 98.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 348024500 0.02% 98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 137644500 0.01% 98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 29219363500 1.54% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1900480571000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.975467 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.617957 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good::kernel 848
-system.cpu1.kern.mode_good::user 572
+system.cpu1.kern.ipl_used::31 0.617919 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good::kernel 850
+system.cpu1.kern.mode_good::user 574
system.cpu1.kern.mode_good::idle 276
system.cpu1.kern.mode_switch::kernel 1766 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 572 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 574 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2543 # number of protection mode switches
-system.cpu1.kern.mode_switch_good::kernel 0.480181 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::kernel 0.481314 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.108533 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 1.588714 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 6310117500 0.33% 0.33% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1035001500 0.05% 0.39% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1893135458000 99.61% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_switch_good::total 1.589847 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 6310376000 0.33% 0.33% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 1022366000 0.05% 0.39% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1893135370000 99.61% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1451 # number of times the context was actually changed
system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed
system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 125 # number of syscalls executed
-system.cpu1.memDep0.conflictingLoads 486173 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 418032 # Number of conflicting stores.
-system.cpu1.memDep0.insertedLoads 2308328 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1509637 # Number of stores inserted to the mem dependence unit.
-system.cpu1.numCycles 19655541 # number of cpu cycles simulated
-system.cpu1.rename.RENAME:BlockCycles 539966 # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps 7148793 # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IQFullEvents 37026 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles 8494445 # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents 255442 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:ROBFullEvents 15493 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.RENAME:RenameLookups 15440476 # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts 12911511 # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands 8475661 # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles 2354555 # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles 305063 # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles 804143 # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps 1326868 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:serializeStallCycles 5655487 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts 515592 # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts 2314825 # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts 52743 # count of temporary serializing insts renamed
-system.cpu1.timesIdled 195289 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.memDep0.conflictingLoads 490785 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 414407 # Number of conflicting stores.
+system.cpu1.memDep0.insertedLoads 2308752 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1509923 # Number of stores inserted to the mem dependence unit.
+system.cpu1.numCycles 19631083 # number of cpu cycles simulated
+system.cpu1.rename.RENAME:BlockCycles 523690 # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps 7148714 # Number of HB maps that are committed
+system.cpu1.rename.RENAME:IQFullEvents 34540 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RENAME:IdleCycles 8495610 # Number of cycles rename is idle
+system.cpu1.rename.RENAME:LSQFullEvents 254592 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RENAME:ROBFullEvents 15458 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.RENAME:RenameLookups 15445784 # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts 12915573 # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands 8478574 # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles 2357052 # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles 305841 # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:UnblockCycles 801048 # Number of cycles rename is unblocking
+system.cpu1.rename.RENAME:UndoneMaps 1329860 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:serializeStallCycles 5654556 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializingInsts 515569 # count of serializing insts renamed
+system.cpu1.rename.RENAME:skidInsts 2305021 # count of insts added to the skid buffer
+system.cpu1.rename.RENAME:tempSerializingInsts 52779 # count of temporary serializing insts renamed
+system.cpu1.timesIdled 194610 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115267.430233 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115273.244186 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 19825998 # number of ReadReq miss cycles
+system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 19826998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1 172 # number of ReadReq misses
system.iocache.ReadReq_misses::total 172 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 10881998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency 10882998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137698.469532 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137691.995716 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85694.888285 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5721646806 # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85688.414469 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5721377806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3560793998 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency 3560524998 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs 6175.166651 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6177.748159 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 64586068 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs 64613068 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137606.001438 # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137599.578276 # average overall miss latency
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85602.434954 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85596.011792 # average overall mshr miss latency
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5741472804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency 5741204804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::1 41724 # number of demand (read+write) misses
system.iocache.demand_misses::total 41724 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3571675996 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency 3571407996 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.029213 # Average percentage of cache occupancy
-system.iocache.occ_blocks::1 0.467409 # Average occupied blocks per context
+system.iocache.occ_%::1 0.029207 # Average percentage of cache occupancy
+system.iocache.occ_blocks::1 0.467307 # Average occupied blocks per context
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137606.001438 # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137599.578276 # average overall miss latency
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85602.434954 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85596.011792 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 5741472804 # number of overall miss cycles
+system.iocache.overall_miss_latency 5741204804 # number of overall miss cycles
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::1 41724 # number of overall misses
system.iocache.overall_misses::total 41724 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3571675996 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 3571407996 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.iocache.replacements 41692 # number of replacements
system.iocache.sampled_refs 41708 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.467409 # Cycle average of tags in use
+system.iocache.tagsinuse 0.467307 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1711286220000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41520 # number of writebacks
-system.l2c.ReadExReq_accesses::0 257299 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 42275 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 299574 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 55985.285399 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 837699.087169 # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0 257314 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1 42271 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 299585 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 55984.756831 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 837468.637532 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40323.891140 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 140918 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 34497 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 175415 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 6515623500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.452318 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 0.183986 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 116381 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 7778 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 124159 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 5006574000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.482548 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 2.936937 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40322.708602 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0 140934 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1 34491 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 175425 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency 6515506000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0 0.452288 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 0.184051 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 116380 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1 7780 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 124160 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 5006467500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0 0.482523 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1 2.937238 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 124159 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 1807451 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 343425 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2150876 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52799.873154 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 3686022.252810 # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses 124160 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0 1807452 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 343469 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2150921 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0 52799.023345 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 3689312.055109 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40018.119229 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40018.019200 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 1503144 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 339066 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1842210 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 16067371000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.168363 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.012693 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 304307 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 4359 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 308666 # number of ReadReq misses
+system.l2c.ReadReq_hits::0 1503148 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 339114 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1842262 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 16066954000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0 0.168361 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.012679 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 304304 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 4355 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 308659 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 12351592500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.170765 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 0.898741 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_latency 12351281500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.170761 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.898605 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 308650 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 840468500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::0 4894.075404 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1 4740.869565 # average SCUpgradeReq miss latency
+system.l2c.ReadReq_mshr_misses 308643 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 840474000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.SCUpgradeReq_accesses::0 607 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1 600 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1207 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_avg_miss_latency::0 4817.117117 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1 4657.665505 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40013.692580 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40013.728964 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_hits::0 52 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1 26 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_miss_latency 2726000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_rate::0 0.914614 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1 0.956739 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0 557 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1 575 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1132 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency 45295500 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.858785 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.883527 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_latency 2673500 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_rate::0 0.914333 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1 0.956667 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_misses::0 555 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1 574 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1129 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_mshr_miss_latency 45175500 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.859967 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.881667 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses 1132 # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0 2884 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 1624 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 4508 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 5854.945055 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 12526.645768 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_mshr_misses 1129 # number of SCUpgradeReq MSHR misses
+system.l2c.UpgradeReq_accesses::0 2880 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 1625 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 4505 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 5822.515585 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 12443.573668 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.724913 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0 154 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 348 # number of UpgradeReq hits
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.987260 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0 153 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1 349 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 502 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 15984000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.946602 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 0.785714 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_latency 15878000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0 0.946875 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 0.785231 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 2727 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1 1276 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 4006 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 160307000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 1.389043 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 2.466749 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::total 4003 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 160188000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0 1.389931 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 2.463385 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 4006 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 4003 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1533340998 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 1533346998 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0 810378 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 810378 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 810378 # number of Writeback hits
system.l2c.Writeback_hits::total 810378 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 5.650924 # Average number of references to valid blocks.
+system.l2c.avg_refs 5.651210 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2064750 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 385700 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 2064766 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 385740 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2450450 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 53681.099770 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 1860673.518992 # average overall miss latency
+system.l2c.demand_accesses::total 2450506 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 53680.339637 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 1860936.135146 # average overall miss latency
system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40105.835368 # average overall mshr miss latency
-system.l2c.demand_hits::0 1644062 # number of demand (read+write) hits
-system.l2c.demand_hits::1 373563 # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency 40105.426718 # average overall mshr miss latency
+system.l2c.demand_hits::0 1644082 # number of demand (read+write) hits
+system.l2c.demand_hits::1 373605 # number of demand (read+write) hits
system.l2c.demand_hits::2 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2017625 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 22582994500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.203748 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.031467 # miss rate for demand accesses
+system.l2c.demand_hits::total 2017687 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 22582460000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0 0.203744 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.031459 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.demand_misses::0 420688 # number of demand (read+write) misses
-system.l2c.demand_misses::1 12137 # number of demand (read+write) misses
+system.l2c.demand_misses::0 420684 # number of demand (read+write) misses
+system.l2c.demand_misses::1 12135 # number of demand (read+write) misses
system.l2c.demand_misses::2 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 432825 # number of demand (read+write) misses
+system.l2c.demand_misses::total 432819 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 17358166500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.209618 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.122139 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency 17357749000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.209614 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 1.122007 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 432809 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses 432803 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.187928 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.005741 # Average percentage of cache occupancy
system.l2c.occ_%::2 0.351843 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 12316.075760 # Average occupied blocks per context
-system.l2c.occ_blocks::1 376.251227 # Average occupied blocks per context
-system.l2c.occ_blocks::2 23058.372205 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2064750 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 385700 # number of overall (read+write) accesses
+system.l2c.occ_blocks::0 12316.028373 # Average occupied blocks per context
+system.l2c.occ_blocks::1 376.255092 # Average occupied blocks per context
+system.l2c.occ_blocks::2 23058.373739 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2064766 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 385740 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2450450 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 53681.099770 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 1860673.518992 # average overall miss latency
+system.l2c.overall_accesses::total 2450506 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 53680.339637 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 1860936.135146 # average overall miss latency
system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40105.835368 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40105.426718 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1644062 # number of overall hits
-system.l2c.overall_hits::1 373563 # number of overall hits
+system.l2c.overall_hits::0 1644082 # number of overall hits
+system.l2c.overall_hits::1 373605 # number of overall hits
system.l2c.overall_hits::2 0 # number of overall hits
-system.l2c.overall_hits::total 2017625 # number of overall hits
-system.l2c.overall_miss_latency 22582994500 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.203748 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.031467 # miss rate for overall accesses
+system.l2c.overall_hits::total 2017687 # number of overall hits
+system.l2c.overall_miss_latency 22582460000 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.203744 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.031459 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 420688 # number of overall misses
-system.l2c.overall_misses::1 12137 # number of overall misses
+system.l2c.overall_misses::0 420684 # number of overall misses
+system.l2c.overall_misses::1 12135 # number of overall misses
system.l2c.overall_misses::2 0 # number of overall misses
-system.l2c.overall_misses::total 432825 # number of overall misses
+system.l2c.overall_misses::total 432819 # number of overall misses
system.l2c.overall_mshr_hits 16 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 17358166500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.209618 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 1.122139 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency 17357749000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.209614 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 1.122007 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 432809 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 2373809498 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses 432803 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 2373820998 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 395557 # number of replacements
-system.l2c.sampled_refs 431639 # Sample count of references to valid blocks.
+system.l2c.replacements 395553 # number of replacements
+system.l2c.sampled_refs 431632 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 35750.699192 # Cycle average of tags in use
-system.l2c.total_refs 2439159 # Total number of references to valid blocks.
+system.l2c.tagsinuse 35750.657204 # Cycle average of tags in use
+system.l2c.total_refs 2439243 # Total number of references to valid blocks.
system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 121360 # number of writebacks
+system.l2c.writebacks 121365 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
All Rights Reserved
-M5 compiled Nov 14 2010 23:49:18
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 14 2010 23:49:28
+M5 compiled Dec 1 2010 12:54:21
+M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
+M5 started Dec 3 2010 12:04:42
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1866702027500 because m5_exit instruction encountered
+Exiting @ tick 1865725201500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 136365 # Simulator instruction rate (inst/s)
-host_mem_usage 291304 # Number of bytes of host memory used
-host_seconds 389.05 # Real time elapsed on the host
-host_tick_rate 4798136047 # Simulator tick rate (ticks/s)
+host_inst_rate 175308 # Simulator instruction rate (inst/s)
+host_mem_usage 291488 # Number of bytes of host memory used
+host_seconds 302.62 # Real time elapsed on the host
+host_tick_rate 6165281708 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 53052455 # Number of instructions simulated
-sim_seconds 1.866702 # Number of seconds simulated
-sim_ticks 1866702027500 # Number of ticks simulated
+sim_insts 53051410 # Number of instructions simulated
+sim_seconds 1.865725 # Number of seconds simulated
+sim_ticks 1865725201500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 6621213 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 12790882 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 40565 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 813829 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 11937472 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 14341052 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1015322 # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches 8457404 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 1008788 # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits 6623532 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 12798498 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 40602 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 812765 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 11935951 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 14337786 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1014820 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 8457292 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 1010049 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 89226144 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.630371 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.393749 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 89220035 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.630402 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.393670 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 65115177 72.98% 72.98% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 10635450 11.92% 84.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 6055707 6.79% 91.68% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 2838740 3.18% 94.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 2097041 2.35% 97.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 703016 0.79% 98.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 396600 0.44% 98.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 375625 0.42% 98.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 1008788 1.13% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 65107302 72.97% 72.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 10633646 11.92% 84.89% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 6059339 6.79% 91.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 2842196 3.19% 94.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 2097639 2.35% 97.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 698987 0.78% 98.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 396440 0.44% 98.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 374437 0.42% 98.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 1010049 1.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 89226144 # Number of insts commited each cycle
-system.cpu.commit.COM:count 56245607 # Number of instructions committed
-system.cpu.commit.COM:loads 9107515 # Number of loads committed
-system.cpu.commit.COM:membars 227978 # Number of memory barriers committed
-system.cpu.commit.COM:refs 15496786 # Number of memory references committed
+system.cpu.commit.COM:committed_per_cycle::total 89220035 # Number of insts commited each cycle
+system.cpu.commit.COM:count 56244494 # Number of instructions committed
+system.cpu.commit.COM:loads 9107208 # Number of loads committed
+system.cpu.commit.COM:membars 227971 # Number of memory barriers committed
+system.cpu.commit.COM:refs 15496285 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 772588 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 56245607 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 667624 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 8707015 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 53052455 # Number of Instructions Simulated
-system.cpu.committedInsts_total 53052455 # Number of Instructions Simulated
-system.cpu.cpi 2.357033 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.357033 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses::0 215727 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 215727 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14718.915641 # average LoadLockedReq miss latency
+system.cpu.commit.branchMispredicts 771538 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 56244494 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 667580 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 8696245 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 53051410 # Number of Instructions Simulated
+system.cpu.committedInsts_total 53051410 # Number of Instructions Simulated
+system.cpu.cpi 2.356931 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.356931 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses::0 215724 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 215724 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14717.635433 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11880.303464 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0 193465 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 193465 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 327672500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103195 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.423892 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0 193462 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 193462 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 327644000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103197 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 22262 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22262 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits 4797 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207489500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080959 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_hits 4800 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207438500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080946 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17465 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 9301609 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9301609 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 22726.604176 # average ReadReq miss latency
+system.cpu.dcache.LoadLockedReq_mshr_misses 17462 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses::0 9298342 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9298342 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 22727.861188 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22780.008433 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.930840 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7726221 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7726221 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 35803219500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.169367 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 1575388 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1575388 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 491526 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 24690385500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0 7723201 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7723201 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 35799586000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0 0.169400 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 1575141 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1575141 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 491284 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 24690187500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116565 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1083862 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906011000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 219693 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 219693 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses 1083857 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906002000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0 219691 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 219691 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits::0 219690 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 219690 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::0 219688 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 219688 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency 42000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_rate::0 0.000014 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses::0 3 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 3 # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::0 6154417 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6154417 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 29746.241624 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses::0 6154235 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6154235 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 29744.201377 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28089.562806 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28089.748800 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 4299174 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4299174 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 55186506550 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.301449 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 1855243 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1855243 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1555600 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 8416840868 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048687 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0 4298938 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4298938 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 55184327582 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0 0.301467 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 1855297 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1855297 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1555651 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 8416980869 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048689 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 299643 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235850498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 8970.438750 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_mshr_misses 299646 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235741498 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 8981.209245 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 8.879414 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 83323 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 8.877118 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 83266 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 747443868 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 747829369 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 15456026 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0 15452577 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15456026 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 26522.737668 # average overall miss latency
+system.cpu.dcache.demand_accesses::total 15452577 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 26522.535484 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23929.965102 # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 12025395 # number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 23929.957773 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0 12022139 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 12025395 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 90989726050 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.221961 # miss rate for demand accesses
+system.cpu.dcache.demand_hits::total 12022139 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 90983913582 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0 0.221998 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 3430631 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 3430438 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3430631 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2047126 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 33107226368 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.089512 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_misses::total 3430438 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2046935 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 33107168369 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0.089532 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1383505 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 1383503 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.995490 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 15456026 # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0 511.995488 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0 15452577 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15456026 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 26522.737668 # average overall miss latency
+system.cpu.dcache.overall_accesses::total 15452577 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 26522.535484 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23929.965102 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23929.957773 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 12025395 # number of overall hits
+system.cpu.dcache.overall_hits::0 12022139 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 12025395 # number of overall hits
-system.cpu.dcache.overall_miss_latency 90989726050 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.221961 # miss rate for overall accesses
+system.cpu.dcache.overall_hits::total 12022139 # number of overall hits
+system.cpu.dcache.overall_miss_latency 90983913582 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0 0.221998 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 3430631 # number of overall misses
+system.cpu.dcache.overall_misses::0 3430438 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 3430631 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2047126 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 33107226368 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0.089512 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_misses::total 3430438 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2046935 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 33107168369 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0 0.089532 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1383505 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 2141861498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_misses 1383503 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 2141743498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1400326 # number of replacements
-system.cpu.dcache.sampled_refs 1400838 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 1400321 # number of replacements
+system.cpu.dcache.sampled_refs 1400833 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.995490 # Cycle average of tags in use
-system.cpu.dcache.total_refs 12438621 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 511.995488 # Cycle average of tags in use
+system.cpu.dcache.total_refs 12435360 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 832750 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 37798869 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 42152 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 613702 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 71408267 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 37495225 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 12847618 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1517170 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 134367 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 1084431 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 1236579 # DTB accesses
-system.cpu.dtb.data_acv 821 # DTB access violations
-system.cpu.dtb.data_hits 16598484 # DTB hits
-system.cpu.dtb.data_misses 46851 # DTB misses
+system.cpu.dcache.writebacks 832778 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 37796755 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 42128 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 613699 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 71391245 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 37490796 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 12847951 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1515207 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 134411 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 1084532 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 1236239 # DTB accesses
+system.cpu.dtb.data_acv 812 # DTB access violations
+system.cpu.dtb.data_hits 16594781 # DTB hits
+system.cpu.dtb.data_misses 46795 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 911643 # DTB read accesses
-system.cpu.dtb.read_acv 587 # DTB read access violations
-system.cpu.dtb.read_hits 10010922 # DTB read hits
-system.cpu.dtb.read_misses 38585 # DTB read misses
-system.cpu.dtb.write_accesses 324936 # DTB write accesses
-system.cpu.dtb.write_acv 234 # DTB write access violations
-system.cpu.dtb.write_hits 6587562 # DTB write hits
-system.cpu.dtb.write_misses 8266 # DTB write misses
-system.cpu.fetch.Branches 14341052 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 8858763 # Number of cache lines fetched
-system.cpu.fetch.Cycles 23012166 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 454758 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 72677531 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 2805 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 885401 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.114686 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 8858763 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 7636535 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.581205 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 90743314 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.800913 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.110485 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.read_accesses 911340 # DTB read accesses
+system.cpu.dtb.read_acv 579 # DTB read access violations
+system.cpu.dtb.read_hits 10007690 # DTB read hits
+system.cpu.dtb.read_misses 38589 # DTB read misses
+system.cpu.dtb.write_accesses 324899 # DTB write accesses
+system.cpu.dtb.write_acv 233 # DTB write access violations
+system.cpu.dtb.write_hits 6587091 # DTB write hits
+system.cpu.dtb.write_misses 8206 # DTB write misses
+system.cpu.fetch.Branches 14337786 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 8855787 # Number of cache lines fetched
+system.cpu.fetch.Cycles 23008954 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 454021 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 72656034 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 2787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 884311 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.114667 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 8855787 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 7638352 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.581069 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 90735242 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.800748 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.110037 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 76629913 84.45% 84.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1043583 1.15% 85.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1968273 2.17% 87.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 922995 1.02% 88.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2983072 3.29% 92.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 649341 0.72% 92.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 774162 0.85% 93.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1071348 1.18% 94.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4700627 5.18% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 76622057 84.45% 84.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1044700 1.15% 85.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1968700 2.17% 87.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 923179 1.02% 88.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2984209 3.29% 92.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 647959 0.71% 92.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 776741 0.86% 93.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1074256 1.18% 94.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4693441 5.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 90743314 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses::0 8858763 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8858763 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14954.289774 # average ReadReq miss latency
+system.cpu.fetch.rateDist::total 90735242 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses::0 8855787 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 8855787 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14954.156504 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.526205 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0 7818580 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7818580 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15555198000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0 0.117419 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 1040183 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1040183 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 47630 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 11849620000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112042 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.651524 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::0 7815574 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7815574 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15555508000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0 0.117461 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0 1040213 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1040213 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 47670 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 11849625000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112078 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 992553 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs 12638.888889 # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_mshr_misses 992543 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs 12375 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 7.878725 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 54 # number of cycles access was blocked
+system.cpu.icache.avg_refs 7.875775 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 682500 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 693000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 8858763 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0 8855787 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8858763 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14954.289774 # average overall miss latency
+system.cpu.icache.demand_accesses::total 8855787 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14954.156504 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11938.526205 # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 7818580 # number of demand (read+write) hits
+system.cpu.icache.demand_avg_mshr_miss_latency 11938.651524 # average overall mshr miss latency
+system.cpu.icache.demand_hits::0 7815574 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7818580 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15555198000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.117419 # miss rate for demand accesses
+system.cpu.icache.demand_hits::total 7815574 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15555508000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0 0.117461 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 1040183 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0 1040213 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1040183 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 47630 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 11849620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.112042 # mshr miss rate for demand accesses
+system.cpu.icache.demand_misses::total 1040213 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 47670 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 11849625000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0 0.112078 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 992553 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.995726 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 509.811580 # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 8858763 # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0 0.995724 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 509.810496 # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0 8855787 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8858763 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14954.289774 # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::0 14954.156504 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11938.526205 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11938.651524 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 7818580 # number of overall hits
+system.cpu.icache.overall_hits::0 7815574 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 7818580 # number of overall hits
-system.cpu.icache.overall_miss_latency 15555198000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.117419 # miss rate for overall accesses
+system.cpu.icache.overall_hits::total 7815574 # number of overall hits
+system.cpu.icache.overall_miss_latency 15555508000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0 0.117461 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 1040183 # number of overall misses
+system.cpu.icache.overall_misses::0 1040213 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 1040183 # number of overall misses
-system.cpu.icache.overall_mshr_hits 47630 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 11849620000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0.112042 # mshr miss rate for overall accesses
+system.cpu.icache.overall_misses::total 1040213 # number of overall misses
+system.cpu.icache.overall_mshr_hits 47670 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 11849625000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0 0.112078 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 992553 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 992543 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 991855 # number of replacements
-system.cpu.icache.sampled_refs 992366 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 991845 # number of replacements
+system.cpu.icache.sampled_refs 992356 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 509.811580 # Cycle average of tags in use
-system.cpu.icache.total_refs 7818579 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 509.810496 # Cycle average of tags in use
+system.cpu.icache.total_refs 7815573 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 24432989000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 92 # number of writebacks
-system.cpu.idleCycles 34303057 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 9120771 # Number of branches executed
-system.cpu.iew.EXEC:nop 3587259 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.457031 # Inst execution rate
-system.cpu.iew.EXEC:refs 16688341 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 6610740 # Number of stores executed
+system.cpu.idleCycles 34303252 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 9120523 # Number of branches executed
+system.cpu.iew.EXEC:nop 3586903 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.457009 # Inst execution rate
+system.cpu.iew.EXEC:refs 16684584 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 6610209 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 35263770 # num instructions consuming a value
-system.cpu.iew.WB:count 56701745 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.757231 # average fanout of values written-back
+system.cpu.iew.WB:consumers 35266489 # num instructions consuming a value
+system.cpu.iew.WB:count 56698013 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.757126 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 26702819 # num instructions producing a value
-system.cpu.iew.WB:rate 0.453446 # insts written-back per cycle
-system.cpu.iew.WB:sent 56803907 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 838873 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 9248148 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 10633496 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 1790322 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 888125 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 6942976 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 65083615 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 10077601 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 523401 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 57150006 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 61281 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 26701175 # num instructions producing a value
+system.cpu.iew.WB:rate 0.453444 # insts written-back per cycle
+system.cpu.iew.WB:sent 56800066 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 837864 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 9247048 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 10627556 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 1790217 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 887680 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 6942367 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 65072200 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 10074375 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 520995 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 57143757 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 61290 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 11748 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1517170 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 557912 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 11719 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1515207 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 557918 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 131935 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 439695 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 9709 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 132136 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 439501 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 9711 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 42652 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 17619 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1525981 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 553705 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 42652 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 406121 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 432752 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.424262 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.424262 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation 42523 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 17618 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1520348 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 553290 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 42523 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 405909 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 431955 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.424281 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.424281 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 39530216 68.54% 68.55% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 62377 0.11% 68.66% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 39528092 68.55% 68.56% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 62364 0.11% 68.67% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 10431492 18.09% 86.80% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659819 11.55% 98.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess 952981 1.65% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.72% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 10425722 18.08% 86.80% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659174 11.55% 98.35% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 952878 1.65% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 57673409 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 436908 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.007576 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 57664754 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 434083 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.007528 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 51858 11.87% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 268470 61.45% 73.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 116580 26.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 49311 11.36% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.36% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 268240 61.79% 73.15% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 116532 26.85% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 90743314 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635566 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200958 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 90735242 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635528 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200743 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 62371115 68.73% 68.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 14052012 15.49% 84.22% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 6227116 6.86% 91.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 3817489 4.21% 95.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 2534919 2.79% 98.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 1095821 1.21% 99.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 467371 0.52% 99.80% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 128077 0.14% 99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 49394 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 62361011 68.73% 68.73% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 14057815 15.49% 84.22% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 6222317 6.86% 91.08% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 3820698 4.21% 95.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 2539136 2.80% 98.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 1090667 1.20% 99.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 464211 0.51% 99.80% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 130030 0.14% 99.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 49357 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 90743314 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.461216 # Inst issue rate
-system.cpu.iq.iqInstsAdded 59456475 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 57673409 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 2039881 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 8066144 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 29810 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 1372257 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 4171431 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 90735242 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.461176 # Inst issue rate
+system.cpu.iq.iqInstsAdded 59445556 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 57664754 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 2039741 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 8057348 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 28990 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 1372161 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 4163419 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 1294967 # ITB accesses
-system.cpu.itb.fetch_acv 915 # ITB acv
-system.cpu.itb.fetch_hits 1255877 # ITB hits
-system.cpu.itb.fetch_misses 39090 # ITB misses
+system.cpu.itb.fetch_accesses 1294712 # ITB accesses
+system.cpu.itb.fetch_acv 931 # ITB acv
+system.cpu.itb.fetch_hits 1255658 # ITB hits
+system.cpu.itb.fetch_misses 39054 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175602 91.19% 93.39% # number of callpals executed
-system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175584 91.19% 93.39% # number of callpals executed
+system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed
+system.cpu.kern.callpal::rti 5222 2.71% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192574 # number of callpals executed
+system.cpu.kern.callpal::total 192554 # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 211736 # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce 6428 # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0 74918 40.95% 40.95% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21 241 0.13% 41.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105906 57.89% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182955 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73551 49.29% 49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73553 49.29% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149235 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1827169522000 97.88% 97.88% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 98068500 0.01% 97.89% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 392034000 0.02% 97.91% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 39041528500 2.09% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1866701153000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981753 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.hwrei 211714 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6425 # number of quiesce instructions executed
+system.cpu.kern.ipl_count::0 74913 40.95% 40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21 242 0.13% 41.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105891 57.88% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182935 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73546 49.28% 49.28% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21 242 0.16% 49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31 73549 49.29% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 149226 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1826194246000 97.88% 97.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 98158000 0.01% 97.89% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 391805000 0.02% 97.91% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 39040113000 2.09% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1865724322000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694512 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good::kernel 1909
-system.cpu.kern.mode_good::user 1739
+system.cpu.kern.ipl_used::31 0.694573 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good::kernel 1907
+system.cpu.kern.mode_good::user 1737
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch::kernel 5963 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2108 # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel 0.320141 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.319805 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.080645 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 1.400786 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 30087907500 1.61% 1.61% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2984190000 0.16% 1.77% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1833629047500 98.23% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total 1.400566 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 30090318500 1.61% 1.61% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2984804000 0.16% 1.77% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1832649191500 98.23% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
-system.cpu.memDep0.conflictingLoads 3017684 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2588344 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 10633496 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6942976 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 125046371 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 13291099 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 38228333 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 1062884 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 39061405 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1660710 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 58609 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 82224860 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 67584077 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 45304633 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 12511976 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1517170 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 4651674 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 7076298 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 19709988 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 1694270 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 11738773 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 247232 # count of temporary serializing insts renamed
-system.cpu.timesIdled 1310674 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.memDep0.conflictingLoads 3016554 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2589214 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 10627556 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6942367 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 125038494 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 13289726 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 38227615 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 1062967 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 39056171 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1660859 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 58584 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 82207964 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 67568741 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 45291881 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 12513158 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1515207 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 4651851 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 7064264 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 19709127 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 1694237 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 11738316 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 247282 # count of temporary serializing insts renamed
+system.cpu.timesIdled 1310688 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115254.323699 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles
+system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137728.913313 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137727.806267 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85725.355699 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5722911806 # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85724.248652 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5722865806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3562059980 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency 3562013980 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs 6166.098893 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6169.439863 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 64596052 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs 64631052 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137635.729275 # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137634.602852 # average overall miss latency
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85632.186411 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85631.059988 # average overall mshr miss latency
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5742850804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency 5742803804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3573002978 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency 3572955978 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.081527 # Average percentage of cache occupancy
-system.iocache.occ_blocks::1 1.304436 # Average occupied blocks per context
+system.iocache.occ_%::1 0.081046 # Average percentage of cache occupancy
+system.iocache.occ_blocks::1 1.296742 # Average occupied blocks per context
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137635.729275 # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137634.602852 # average overall miss latency
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85632.186411 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85631.059988 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 5742850804 # number of overall miss cycles
+system.iocache.overall_miss_latency 5742803804 # number of overall miss cycles
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::1 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3573002978 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 3572955978 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.iocache.replacements 41685 # number of replacements
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.304436 # Cycle average of tags in use
+system.iocache.tagsinuse 1.296742 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1711281439000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
-system.l2c.ReadExReq_accesses::0 300869 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 300869 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52487.240298 # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0 300867 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 300867 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52486.783520 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40337.781709 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 183860 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 183860 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 6141479500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.388903 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 117009 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 117009 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 4719883500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.388903 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40337.693248 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0 183854 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 183854 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency 6141636000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0 0.388919 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 117013 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 117013 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 4720034500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0 0.388919 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 117009 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 2092408 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2092408 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52046.041420 # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses 117013 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0 2092394 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2092394 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0 52046.378325 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40014.986194 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40015.178174 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 1784924 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1784924 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 16003325000 # number of ReadReq miss cycles
+system.l2c.ReadReq_hits::0 1784912 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1784912 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 16003324500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.146952 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 307484 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 307484 # number of ReadReq misses
+system.l2c.ReadReq_misses::0 307482 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 307482 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 12303928000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency 12303907000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.146952 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 307483 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 811377500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_misses 307481 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 811370500 # number of ReadReq MSHR uncacheable cycles
system.l2c.SCUpgradeReq_accesses::0 3 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1116250998 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 832842 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 832842 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 832842 # number of Writeback hits
-system.l2c.Writeback_hits::total 832842 # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency 1116153998 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0 832870 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 832870 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 832870 # number of Writeback hits
+system.l2c.Writeback_hits::total 832870 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 5.630753 # Average number of references to valid blocks.
+system.l2c.avg_refs 5.629899 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2393277 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 2393261 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2393277 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52167.655297 # average overall miss latency
+system.l2c.demand_accesses::total 2393261 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 52167.777006 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40103.963090 # average overall mshr miss latency
-system.l2c.demand_hits::0 1968784 # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency 40104.080387 # average overall mshr miss latency
+system.l2c.demand_hits::0 1968766 # number of demand (read+write) hits
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1968784 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 22144804500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.177369 # miss rate for demand accesses
+system.l2c.demand_hits::total 1968766 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 22144960500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0 0.177371 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.demand_misses::0 424493 # number of demand (read+write) misses
+system.l2c.demand_misses::0 424495 # number of demand (read+write) misses
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 424493 # number of demand (read+write) misses
+system.l2c.demand_misses::total 424495 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 17023811500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.177369 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency 17023941500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.177371 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 424492 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses 424494 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.186929 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.344699 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 12250.608437 # Average occupied blocks per context
-system.l2c.occ_blocks::1 22590.202953 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2393277 # number of overall (read+write) accesses
+system.l2c.occ_%::0 0.186894 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.344697 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 12248.264673 # Average occupied blocks per context
+system.l2c.occ_blocks::1 22590.041641 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2393261 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2393277 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52167.655297 # average overall miss latency
+system.l2c.overall_accesses::total 2393261 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 52167.777006 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40103.963090 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40104.080387 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1968784 # number of overall hits
+system.l2c.overall_hits::0 1968766 # number of overall hits
system.l2c.overall_hits::1 0 # number of overall hits
-system.l2c.overall_hits::total 1968784 # number of overall hits
-system.l2c.overall_miss_latency 22144804500 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.177369 # miss rate for overall accesses
+system.l2c.overall_hits::total 1968766 # number of overall hits
+system.l2c.overall_miss_latency 22144960500 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.177371 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 424493 # number of overall misses
+system.l2c.overall_misses::0 424495 # number of overall misses
system.l2c.overall_misses::1 0 # number of overall misses
-system.l2c.overall_misses::total 424493 # number of overall misses
+system.l2c.overall_misses::total 424495 # number of overall misses
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 17023811500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.177369 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency 17023941500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.177371 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 424492 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 1927628498 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses 424494 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1927524498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 390990 # number of replacements
-system.l2c.sampled_refs 423735 # Sample count of references to valid blocks.
+system.l2c.replacements 390994 # number of replacements
+system.l2c.sampled_refs 423736 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 34840.811390 # Cycle average of tags in use
-system.l2c.total_refs 2385947 # Total number of references to valid blocks.
+system.l2c.tagsinuse 34838.306314 # Cycle average of tags in use
+system.l2c.total_refs 2385591 # Total number of references to valid blocks.
system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 117624 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
All Rights Reserved
-M5 compiled Nov 15 2010 00:04:22
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 15 2010 00:04:25
+M5 compiled Dec 2 2010 15:11:52
+M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
+M5 started Dec 2 2010 19:10:47
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 18639500 because target called exit()
+Exiting @ tick 18731500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 33758 # Simulator instruction rate (inst/s)
-host_mem_usage 203840 # Number of bytes of host memory used
-host_seconds 0.43 # Real time elapsed on the host
-host_tick_rate 43520237 # Simulator tick rate (ticks/s)
+host_inst_rate 90431 # Simulator instruction rate (inst/s)
+host_mem_usage 203888 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
+host_tick_rate 117038227 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 18639500 # Number of ticks simulated
+sim_ticks 18731500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 2677 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 5066 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 2701 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 5096 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 725 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 5166 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 5166 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 5196 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 5196 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 3359 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 84 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 27536 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.551097 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.189203 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 27718 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.547478 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.185032 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 19764 71.78% 71.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 4506 16.36% 88.14% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 1459 5.30% 93.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 767 2.79% 96.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 365 1.33% 97.55% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 265 0.96% 98.51% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 289 1.05% 99.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.69% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 84 0.31% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 19937 71.93% 71.93% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 4515 16.29% 88.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 1459 5.26% 93.48% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 767 2.77% 96.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 374 1.35% 97.60% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 256 0.92% 98.52% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 289 1.04% 99.56% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 84 0.30% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 27536 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 27718 # Number of insts commited each cycle
system.cpu.commit.COM:count 15175 # Number of instructions committed
system.cpu.commit.COM:loads 2226 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.branchMispredicts 725 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4917 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5217 # The number of squashed insts skipped by commit
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
-system.cpu.cpi 2.580109 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.580109 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 2725 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 33508.064516 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35587.301587 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2601 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4155000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.045505 # miss rate for ReadReq accesses
+system.cpu.cpi 2.592844 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.592844 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 2789 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33620.967742 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35563.492063 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2665 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4169000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.044460 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2242000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.023119 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2240500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.022589 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35792.892157 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.060241 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 35892.156863 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35843.373494 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 14603500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 14644000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2968500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2975000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 24.938356 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 25.376712 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 4167 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 35260.338346 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35688.356164 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 3635 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 18758500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.127670 # miss rate for demand accesses
+system.cpu.dcache.demand_accesses 4231 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 35362.781955 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 3699 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 18813000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.125739 # miss rate for demand accesses
system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5210500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.035037 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_latency 5215500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.034507 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.024989 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 102.354840 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 4167 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 35260.338346 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35688.356164 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.024963 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 102.247340 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 4231 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 35362.781955 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35722.602740 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 3635 # number of overall hits
-system.cpu.dcache.overall_miss_latency 18758500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.127670 # miss rate for overall accesses
+system.cpu.dcache.overall_hits 3699 # number of overall hits
+system.cpu.dcache.overall_miss_latency 18813000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.125739 # miss rate for overall accesses
system.cpu.dcache.overall_misses 532 # number of overall misses
system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5210500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.035037 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_latency 5215500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.034507 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 102.354840 # Cycle average of tags in use
-system.cpu.dcache.total_refs 3641 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 102.247340 # Cycle average of tags in use
+system.cpu.dcache.total_refs 3705 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 7103 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 23378 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 13089 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 7237 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1142 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:BlockedCycles 7118 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 23678 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 13190 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 7286 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1191 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 5166 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 4063 # Number of cache lines fetched
-system.cpu.fetch.Cycles 11559 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 23733 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 820 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.138573 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 4063 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 2677 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.636615 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 28678 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.827568 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.939691 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches 5196 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 4112 # Number of cache lines fetched
+system.cpu.fetch.Cycles 11672 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 24093 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 837 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.138693 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 4112 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 2701 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.643097 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 28892 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.833899 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.950141 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 21209 73.96% 73.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3590 12.52% 86.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 580 2.02% 88.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 498 1.74% 90.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 667 2.33% 92.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 529 1.84% 94.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 243 0.85% 95.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 178 0.62% 95.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1184 4.13% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21359 73.93% 73.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3597 12.45% 86.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 580 2.01% 88.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 513 1.78% 90.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 668 2.31% 92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 530 1.83% 94.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 244 0.84% 95.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 197 0.68% 95.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1204 4.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 28678 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 4063 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 34748.459959 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34876.056338 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 3576 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 16922500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.119862 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 487 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 12381000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.087374 # mshr miss rate for ReadReq accesses
+system.cpu.fetch.rateDist::total 28892 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 4112 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 34753.073770 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34880.281690 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 3624 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16959500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.118677 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 488 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 133 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 12382500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.086333 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 355 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 10.101695 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 10.237288 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 4063 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 34748.459959 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34876.056338 # average overall mshr miss latency
-system.cpu.icache.demand_hits 3576 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16922500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.119862 # miss rate for demand accesses
-system.cpu.icache.demand_misses 487 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 12381000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.087374 # mshr miss rate for demand accesses
+system.cpu.icache.demand_accesses 4112 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 34753.073770 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34880.281690 # average overall mshr miss latency
+system.cpu.icache.demand_hits 3624 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16959500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.118677 # miss rate for demand accesses
+system.cpu.icache.demand_misses 488 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 12382500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.086333 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 355 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.100082 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 204.967174 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 4063 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 34748.459959 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34876.056338 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.099925 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 204.645792 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 4112 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 34753.073770 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34880.281690 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 3576 # number of overall hits
-system.cpu.icache.overall_miss_latency 16922500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.119862 # miss rate for overall accesses
-system.cpu.icache.overall_misses 487 # number of overall misses
-system.cpu.icache.overall_mshr_hits 132 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 12381000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.087374 # mshr miss rate for overall accesses
+system.cpu.icache.overall_hits 3624 # number of overall hits
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+system.cpu.icache.overall_miss_rate 0.118677 # miss rate for overall accesses
+system.cpu.icache.overall_misses 488 # number of overall misses
+system.cpu.icache.overall_mshr_hits 133 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 12382500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.086333 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 355 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 204.967174 # Cycle average of tags in use
-system.cpu.icache.total_refs 3576 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 204.645792 # Cycle average of tags in use
+system.cpu.icache.total_refs 3624 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 8602 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 8572 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 3845 # Number of branches executed
system.cpu.iew.EXEC:nop 1083 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.467838 # Inst execution rate
-system.cpu.iew.EXEC:refs 4472 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1661 # Number of stores executed
+system.cpu.iew.EXEC:rate 0.470131 # Inst execution rate
+system.cpu.iew.EXEC:refs 4644 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1769 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 9394 # num instructions consuming a value
-system.cpu.iew.WB:count 17034 # cumulative count of insts written-back
+system.cpu.iew.WB:count 17150 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.855972 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 8041 # num instructions producing a value
-system.cpu.iew.WB:rate 0.456921 # insts written-back per cycle
-system.cpu.iew.WB:sent 17187 # cumulative count of insts sent to commit
+system.cpu.iew.WB:rate 0.457773 # insts written-back per cycle
+system.cpu.iew.WB:sent 17335 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 821 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2960 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 3080 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 569 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1800 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 20159 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 2811 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 446 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 17441 # Number of executed instructions
+system.cpu.iew.iewDispStoreInsts 1935 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 20414 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 2875 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 481 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 17613 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1142 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 1191 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 734 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 352 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 854 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 487 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 582 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 239 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.387580 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.387580 # IPC: Total IPC of All Threads
+system.cpu.ipc 0.385677 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.385677 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 13329 74.52% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 74.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 2869 16.04% 90.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 1689 9.44% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 13329 73.67% 73.67% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 17887 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 88 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.004920 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 18094 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 123 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.006798 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 26 29.55% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 29.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 21 23.86% 53.41% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 41 46.59% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 26 21.14% 21.14% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 28678 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.623719 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.187639 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 28892 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.626263 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.192032 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 19867 69.28% 69.28% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 4247 14.81% 84.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 1908 6.65% 90.74% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 1720 6.00% 96.74% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 389 1.36% 98.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 20022 69.30% 69.30% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 4253 14.72% 84.02% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 1909 6.61% 90.63% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 1729 5.98% 96.61% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 432 1.50% 98.11% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 282 0.98% 99.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 171 0.60% 99.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 171 0.59% 99.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 80 0.28% 99.95% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 28678 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.479802 # Inst issue rate
-system.cpu.iq.iqInstsAdded 18507 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 17887 # Number of instructions issued
+system.cpu.iq.ISSUE:issued_per_cycle::total 28892 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.482970 # Inst issue rate
+system.cpu.iq.iqInstsAdded 18762 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 18094 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 569 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3884 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 28 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4139 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 3281 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 3725 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.144578 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31409.638554 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2866500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.385542 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2871500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2607000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 418 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34231.884058 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.038647 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34234.299517 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.454106 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14172000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 14173000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990431 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 414 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12836500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12837500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990431 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 414 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 501 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34282.696177 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.440644 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34294.768612 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31082.494970 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 17038500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 17044500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992016 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 15443500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 15448000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992016 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 497 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.007304 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 239.321987 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.007292 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 238.958608 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 501 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34282.696177 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.440644 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34294.768612 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31082.494970 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 17038500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 17044500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992016 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 497 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 15443500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 15448000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992016 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 497 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 239.321987 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 238.958608 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 2960 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1800 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 37280 # number of cpu cycles simulated
+system.cpu.memDep0.insertedLoads 3080 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1935 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 37464 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 13548 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 13649 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 39844 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 21594 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 19316 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 7011 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1142 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:RenameLookups 40984 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 21894 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 19600 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 7060 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1191 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 422 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 5484 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 6301 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 607 # count of serializing insts renamed
+system.cpu.rename.RENAME:UndoneMaps 5768 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 6316 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 622 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2701 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 587 # count of temporary serializing insts renamed
-system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Nov 15 2010 00:04:22
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 15 2010 00:06:46
+M5 compiled Dec 2 2010 15:11:52
+M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
+M5 started Dec 2 2010 19:11:11
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
Iteration 10 completed
PASSED :-)
-Exiting @ tick 117567000 because target called exit()
+Exiting @ tick 117665000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 225525 # Simulator instruction rate (inst/s)
-host_mem_usage 214280 # Number of bytes of host memory used
-host_seconds 5.12 # Real time elapsed on the host
-host_tick_rate 22978978 # Simulator tick rate (ticks/s)
+host_inst_rate 152094 # Simulator instruction rate (inst/s)
+host_mem_usage 214340 # Number of bytes of host memory used
+host_seconds 7.59 # Real time elapsed on the host
+host_tick_rate 15507555 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1153797 # Number of instructions simulated
+sim_insts 1153987 # Number of instructions simulated
sim_seconds 0.000118 # Number of seconds simulated
-sim_ticks 117567000 # Number of ticks simulated
+sim_ticks 117665000 # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits 89355 # Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups 91985 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 89393 # Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups 92028 # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect 1075 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted 92438 # Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups 92438 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 92481 # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups 92481 # Number of BP lookups
system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches 89649 # Number of branches committed
+system.cpu0.commit.COM:branches 89667 # Number of branches committed
system.cpu0.commit.COM:bw_lim_events 218 # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples 214956 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean 2.489454 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev 2.121443 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples 215178 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean 2.487387 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev 2.121699 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0 33666 15.66% 15.66% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1 90734 42.21% 57.87% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2 2490 1.16% 59.03% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3 739 0.34% 59.37% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4 734 0.34% 59.72% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5 85813 39.92% 99.64% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0 33843 15.73% 15.73% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1 90761 42.18% 57.91% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2 2490 1.16% 59.06% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3 739 0.34% 59.41% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4 743 0.35% 59.75% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5 85822 39.88% 99.64% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6 487 0.23% 99.86% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7 75 0.03% 99.90% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8 218 0.10% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total 214956 # Number of insts commited each cycle
-system.cpu0.commit.COM:count 535123 # Number of instructions committed
-system.cpu0.commit.COM:loads 174510 # Number of loads committed
+system.cpu0.commit.COM:committed_per_cycle::total 215178 # Number of insts commited each cycle
+system.cpu0.commit.COM:count 535231 # Number of instructions committed
+system.cpu0.commit.COM:loads 174546 # Number of loads committed
system.cpu0.commit.COM:membars 84 # Number of memory barriers committed
-system.cpu0.commit.COM:refs 262271 # Number of memory references committed
+system.cpu0.commit.COM:refs 262325 # Number of memory references committed
system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts 1075 # The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts 535123 # The number of committed instructions
+system.cpu0.commit.commitCommittedInsts 535231 # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts 9238 # The number of squashed insts skipped by commit
-system.cpu0.committedInsts 448659 # Number of Instructions Simulated
-system.cpu0.committedInsts_total 448659 # Number of Instructions Simulated
-system.cpu0.cpi 0.524084 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.524084 # CPI: Total CPI of All Threads
-system.cpu0.dcache.ReadReq_accesses 89545 # number of ReadReq accesses(hits+misses)
+system.cpu0.commit.commitSquashedInsts 9532 # The number of squashed insts skipped by commit
+system.cpu0.committedInsts 448749 # Number of Instructions Simulated
+system.cpu0.committedInsts_total 448749 # Number of Instructions Simulated
+system.cpu0.cpi 0.524416 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.524416 # CPI: Total CPI of All Threads
+system.cpu0.dcache.ReadReq_accesses 89627 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 27580.808081 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27913.043478 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_hits 89050 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits 89132 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency 13652500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.005528 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate 0.005523 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 495 # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits 311 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency 5136000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002055 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002053 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses
system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_avg_miss_latency 16596.153846 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_mshr_miss_latency 353500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 87719 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 46114.070501 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37094.827586 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 87180 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 24855484 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.006145 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 539 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits 365 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency 6454500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001984 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_accesses 87737 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 46115.711111 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37137.931034 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_hits 87197 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 24902484 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.006155 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits 366 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency 6462000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.001983 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 639.867816 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 640.367816 # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 177264 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 37241.764023 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 32375.698324 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 176230 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 38507984 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.005833 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 1034 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 676 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 11590500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.002020 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_accesses 177364 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 37251.192271 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 32396.648045 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 176329 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 38554984 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.005835 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 1035 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 677 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 11598000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.002018 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.276057 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1 -0.002702 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 141.341435 # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1 -1.383203 # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses 177264 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 37241.764023 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 32375.698324 # average overall mshr miss latency
+system.cpu0.dcache.occ_%::0 0.275981 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_%::1 -0.002700 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0 141.302499 # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1 -1.382442 # Average occupied blocks per context
+system.cpu0.dcache.overall_accesses 177364 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 37251.192271 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 32396.648045 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 176230 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 38507984 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.005833 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 1034 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 676 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 11590500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.002020 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_hits 176329 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 38554984 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.005835 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 1035 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 677 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 11598000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.002018 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements 9 # number of replacements
system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 139.958233 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 111337 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 139.920057 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 111424 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 6 # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles 13605 # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:DecodedInsts 549348 # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles 19922 # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles 181227 # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles 2012 # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:BlockedCycles 13620 # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:DecodedInsts 549750 # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles 20029 # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles 181310 # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles 2059 # Number of cycles decode is squashing
system.cpu0.decode.DECODE:UnblockCycles 202 # Number of cycles decode is unblocking
-system.cpu0.fetch.Branches 92438 # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines 5211 # Number of cache lines fetched
-system.cpu0.fetch.Cycles 186910 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes 478 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts 550298 # Number of instructions fetch has processed
-system.cpu0.fetch.SquashCycles 1215 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate 0.393127 # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles 5211 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.predictedBranches 89355 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate 2.340349 # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist::samples 216968 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.536310 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.185886 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.Branches 92481 # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines 5258 # Number of cache lines fetched
+system.cpu0.fetch.Cycles 187053 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes 482 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts 550749 # Number of instructions fetch has processed
+system.cpu0.fetch.SquashCycles 1232 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate 0.392983 # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles 5258 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches 89393 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate 2.340316 # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::samples 217220 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.535443 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.186868 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 35310 16.27% 16.27% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 90281 41.61% 57.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 487 0.22% 58.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 792 0.37% 58.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 586 0.27% 58.74% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 86643 39.93% 98.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 826 0.38% 99.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 192 0.09% 99.15% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 1851 0.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 35466 16.33% 16.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 90305 41.57% 57.90% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 487 0.22% 58.12% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 806 0.37% 58.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 587 0.27% 58.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 86662 39.90% 98.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 826 0.38% 99.04% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 210 0.10% 99.14% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 1871 0.86% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 216968 # Number of instructions fetched each cycle (Total)
-system.cpu0.icache.ReadReq_accesses 5211 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 39190.412783 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37010.673235 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 4460 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 29432000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.144118 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 751 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits 142 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_miss_latency 22539500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.116868 # mshr miss rate for ReadReq accesses
+system.cpu0.fetch.rateDist::total 217220 # Number of instructions fetched each cycle (Total)
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system.cpu0.icache.ReadReq_mshr_misses 609 # number of ReadReq MSHR misses
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system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs 22000 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 5211 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 39190.412783 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 37010.673235 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 4460 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 29432000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.144118 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 751 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 142 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 22539500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.116868 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_accesses 5258 # number of demand (read+write) accesses
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system.cpu0.icache.demand_mshr_misses 609 # number of demand (read+write) MSHR misses
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 4460 # number of overall hits
-system.cpu0.icache.overall_miss_latency 29432000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.144118 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 751 # number of overall misses
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-system.cpu0.icache.overall_mshr_miss_latency 22539500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.116868 # mshr miss rate for overall accesses
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system.cpu0.icache.overall_mshr_misses 609 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements 307 # number of replacements
system.cpu0.icache.sampled_refs 608 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 257.575944 # Cycle average of tags in use
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system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
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-system.cpu0.iew.EXEC:branches 90443 # Number of branches executed
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system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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-system.cpu0.iew.WB:sent 453963 # cumulative count of insts sent to commit
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+system.cpu0.iew.WB:sent 454201 # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts 1256 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles 901 # Number of cycles IEW is blocking
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system.cpu0.iew.iewDispNonSpecInsts 725 # Number of dispatched non-speculative instructions
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system.cpu0.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.iewSquashCycles 2012 # Number of cycles IEW is squashing
+system.cpu0.iew.iewSquashCycles 2059 # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
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system.cpu0.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation 74 # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
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system.cpu0.iew.memOrderViolationEvents 74 # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect 831 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly
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-system.cpu0.ipc_total 1.908091 # IPC: Total IPC of All Threads
+system.cpu0.ipc 1.906884 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.906884 # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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-system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 15.76% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead 75 40.76% 56.52% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite 80 43.48% 100.00% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntAlu 29 13.24% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 13.24% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemRead 83 37.90% 51.14% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemWrite 107 48.86% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples 216968 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean 2.098074 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.056367 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::samples 217220 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::mean 2.097008 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.057658 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0 33344 15.37% 15.37% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1 5639 2.60% 17.97% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2 88266 40.68% 58.65% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3 87233 40.21% 98.85% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4 1475 0.68% 99.53% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5 727 0.34% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::0 33500 15.42% 15.42% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::1 5647 2.60% 18.02% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::2 88284 40.64% 58.66% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::3 87260 40.17% 98.84% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::4 1518 0.70% 99.53% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::5 727 0.33% 99.87% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6 185 0.09% 99.95% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7 92 0.04% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8 7 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total 216968 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate 1.935973 # Inst issue rate
-system.cpu0.iq.iqInstsAdded 456737 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqInstsIssued 455215 # Number of instructions issued
+system.cpu0.iq.ISSUE:issued_per_cycle::total 217220 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:rate 1.935623 # Inst issue rate
+system.cpu0.iq.iqInstsAdded 457082 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued 455512 # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded 822 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined 7989 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 8244 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved 263 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.iqSquashedOperandsExamined 6440 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.memDep0.conflictingLoads 86348 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 86194 # Number of conflicting stores.
-system.cpu0.memDep0.insertedLoads 176074 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 88705 # Number of stores inserted to the mem dependence unit.
-system.cpu0.numCycles 235135 # number of cpu cycles simulated
+system.cpu0.iq.iqSquashedOperandsExamined 6884 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.memDep0.conflictingLoads 86366 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 86212 # Number of conflicting stores.
+system.cpu0.memDep0.insertedLoads 176230 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 88858 # Number of stores inserted to the mem dependence unit.
+system.cpu0.numCycles 235331 # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles 1287 # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps 361852 # Number of HB maps that are committed
+system.cpu0.rename.RENAME:CommittedMaps 361924 # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles 20610 # Number of cycles rename is idle
+system.cpu0.rename.RENAME:IdleCycles 20717 # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents 290 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:RenameLookups 1089678 # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts 546179 # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands 371907 # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles 180783 # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles 2012 # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:RenameLookups 1091002 # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts 546581 # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands 372241 # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles 180866 # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles 2059 # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles 696 # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps 10055 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:serializeStallCycles 11580 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts 797 # count of serializing insts renamed
+system.cpu0.rename.RENAME:UndoneMaps 10317 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:serializeStallCycles 11595 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts 810 # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts 4205 # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts 813 # count of temporary serializing insts renamed
-system.cpu0.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.timesIdled 337 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.BTBHits 54161 # Number of BTB hits
-system.cpu1.BPredUnit.BTBLookups 56395 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 54164 # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups 56398 # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect 1087 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.condPredicted 56507 # Number of conditional branches predicted
-system.cpu1.BPredUnit.lookups 56507 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 56510 # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups 56510 # Number of BP lookups
system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches 53696 # Number of branches committed
+system.cpu1.commit.COM:branches 53699 # Number of branches committed
system.cpu1.commit.COM:bw_lim_events 485 # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples 188473 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean 1.608787 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev 1.965463 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::samples 188517 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::mean 1.608476 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::stdev 1.965365 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0 76772 40.73% 40.73% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1 54519 28.93% 69.66% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2 7469 3.96% 73.62% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3 7244 3.84% 77.47% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4 2460 1.31% 78.77% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5 38973 20.68% 99.45% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::0 76809 40.74% 40.74% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::1 54523 28.92% 69.67% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::2 7469 3.96% 73.63% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::3 7247 3.84% 77.47% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::4 2461 1.31% 78.78% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::5 38972 20.67% 99.45% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6 418 0.22% 99.67% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7 133 0.07% 99.74% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8 485 0.26% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total 188473 # Number of insts commited each cycle
-system.cpu1.commit.COM:count 303213 # Number of instructions committed
-system.cpu1.commit.COM:loads 89248 # Number of loads committed
-system.cpu1.commit.COM:membars 5702 # Number of memory barriers committed
-system.cpu1.commit.COM:refs 131277 # Number of memory references committed
+system.cpu1.commit.COM:committed_per_cycle::total 188517 # Number of insts commited each cycle
+system.cpu1.commit.COM:count 303225 # Number of instructions committed
+system.cpu1.commit.COM:loads 89251 # Number of loads committed
+system.cpu1.commit.COM:membars 5705 # Number of memory barriers committed
+system.cpu1.commit.COM:refs 131280 # Number of memory references committed
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts 1087 # The number of times a branch was mispredicted
-system.cpu1.commit.commitCommittedInsts 303213 # The number of committed instructions
-system.cpu1.commit.commitNonSpecStalls 6416 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.commitSquashedInsts 8260 # The number of squashed insts skipped by commit
-system.cpu1.committedInsts 253025 # Number of Instructions Simulated
-system.cpu1.committedInsts_total 253025 # Number of Instructions Simulated
-system.cpu1.cpi 0.791222 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.791222 # CPI: Total CPI of All Threads
-system.cpu1.dcache.ReadReq_accesses 51822 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 22047.619048 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13770.186335 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_hits 51360 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 10186000 # number of ReadReq miss cycles
+system.cpu1.commit.commitCommittedInsts 303225 # The number of committed instructions
+system.cpu1.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.commitSquashedInsts 8275 # The number of squashed insts skipped by commit
+system.cpu1.committedInsts 253031 # Number of Instructions Simulated
+system.cpu1.committedInsts_total 253031 # Number of Instructions Simulated
+system.cpu1.cpi 0.791401 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.791401 # CPI: Total CPI of All Threads
+system.cpu1.dcache.ReadReq_accesses 51825 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 22044.372294 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13760.869565 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_hits 51363 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 10184500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate 0.008915 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 462 # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency 2217000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency 2215500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003107 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses 161 # number of ReadReq MSHR misses
system.cpu1.dcache.SwapReq_accesses 68 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_mshr_miss_rate 0.823529 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_misses 56 # number of SwapReq MSHR misses
system.cpu1.dcache.WriteReq_accesses 41961 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 22916 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency 22944 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14406.542056 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_hits 41836 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 2864500 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency 2868000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate 0.002979 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses 125 # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 93783 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 22232.538330 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 14024.253731 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 93196 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 13050500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_accesses 93786 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 22235.945486 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 14018.656716 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 93199 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 13052500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate 0.006259 # miss rate for demand accesses
system.cpu1.dcache.demand_misses 587 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 3758500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency 3757000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0.002858 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses 268 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.047229 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_%::1 -0.018864 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0 24.181003 # Average occupied blocks per context
-system.cpu1.dcache.occ_blocks::1 -9.658476 # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses 93783 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 22232.538330 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 14024.253731 # average overall mshr miss latency
+system.cpu1.dcache.occ_%::0 0.047197 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_%::1 -0.018851 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0 24.164747 # Average occupied blocks per context
+system.cpu1.dcache.occ_blocks::1 -9.651740 # Average occupied blocks per context
+system.cpu1.dcache.overall_accesses 93786 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 22235.945486 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 14018.656716 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 93196 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 13050500 # number of overall miss cycles
+system.cpu1.dcache.overall_hits 93199 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 13052500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate 0.006259 # miss rate for overall accesses
system.cpu1.dcache.overall_misses 587 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 319 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 3758500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency 3757000 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0.002858 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses 268 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.replacements 2 # number of replacements
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 14.522528 # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse 14.513007 # Cycle average of tags in use
system.cpu1.dcache.total_refs 47800 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 1 # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles 20776 # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:DecodedInsts 315521 # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles 53573 # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles 108896 # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles 1776 # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:UnblockCycles 5228 # Number of cycles decode is unblocking
-system.cpu1.fetch.Branches 56507 # Number of branches that fetch encountered
-system.cpu1.fetch.CacheLines 20124 # Number of cache lines fetched
-system.cpu1.fetch.Cycles 134645 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.Insts 316659 # Number of instructions fetch has processed
-system.cpu1.fetch.SquashCycles 1165 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate 0.282254 # Number of branch fetches per cycle
-system.cpu1.fetch.icacheStallCycles 20124 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.predictedBranches 54161 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate 1.581721 # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist::samples 196865 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.608508 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.050886 # Number of instructions fetched each cycle (Total)
+system.cpu1.decode.DECODE:BlockedCycles 20785 # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:DecodedInsts 315548 # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles 53596 # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles 108904 # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles 1778 # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:UnblockCycles 5231 # Number of cycles decode is unblocking
+system.cpu1.fetch.Branches 56510 # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines 20132 # Number of cache lines fetched
+system.cpu1.fetch.Cycles 134664 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes 220 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts 316686 # Number of instructions fetch has processed
+system.cpu1.fetch.SquashCycles 1166 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate 0.282199 # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles 20132 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches 54164 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate 1.581461 # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::samples 196924 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.608164 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.050823 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 82366 41.84% 41.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 58899 29.92% 71.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 6765 3.44% 75.19% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 2772 1.41% 76.60% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1900 0.97% 77.57% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 39920 20.28% 97.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 82414 41.85% 41.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 58905 29.91% 71.76% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 6768 3.44% 75.20% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 2772 1.41% 76.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1900 0.96% 77.57% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 39920 20.27% 97.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 2488 1.26% 99.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 254 0.13% 99.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 1501 0.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 255 0.13% 99.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 1502 0.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 196865 # Number of instructions fetched each cycle (Total)
-system.cpu1.icache.ReadReq_accesses 20124 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 15227.650728 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12284.753363 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits 19643 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 7324500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate 0.023902 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 481 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_miss_latency 5479000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.022163 # mshr miss rate for ReadReq accesses
+system.cpu1.fetch.rateDist::total 196924 # Number of instructions fetched each cycle (Total)
+system.cpu1.icache.ReadReq_accesses 20132 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 15221.991701 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12289.237668 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits 19650 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency 7337000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate 0.023942 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 482 # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_hits 36 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_miss_latency 5481000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate 0.022154 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses 446 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 44.042601 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 44.058296 # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 20124 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 15227.650728 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 12284.753363 # average overall mshr miss latency
-system.cpu1.icache.demand_hits 19643 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 7324500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.023902 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 481 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 5479000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0.022163 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_accesses 20132 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 15221.991701 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 12289.237668 # average overall mshr miss latency
+system.cpu1.icache.demand_hits 19650 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 7337000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.023942 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 482 # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits 36 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency 5481000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0.022154 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0 0.166563 # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0 85.280274 # Average occupied blocks per context
-system.cpu1.icache.overall_accesses 20124 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 15227.650728 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 12284.753363 # average overall mshr miss latency
+system.cpu1.icache.occ_%::0 0.166450 # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::0 85.222348 # Average occupied blocks per context
+system.cpu1.icache.overall_accesses 20132 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 15221.991701 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 12289.237668 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 19643 # number of overall hits
-system.cpu1.icache.overall_miss_latency 7324500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.023902 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 481 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 35 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 5479000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0.022163 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_hits 19650 # number of overall hits
+system.cpu1.icache.overall_miss_latency 7337000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.023942 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 482 # number of overall misses
+system.cpu1.icache.overall_mshr_hits 36 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency 5481000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0.022154 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses 446 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements 334 # number of replacements
system.cpu1.icache.sampled_refs 446 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 85.280274 # Cycle average of tags in use
-system.cpu1.icache.total_refs 19643 # Total number of references to valid blocks.
+system.cpu1.icache.tagsinuse 85.222348 # Cycle average of tags in use
+system.cpu1.icache.total_refs 19650 # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idleCycles 3334 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches 54256 # Number of branches executed
-system.cpu1.iew.EXEC:nop 45272 # number of nop insts executed
-system.cpu1.iew.EXEC:rate 1.311145 # Inst execution rate
-system.cpu1.iew.EXEC:refs 132363 # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores 42366 # Number of stores executed
+system.cpu1.idleCycles 3325 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches 54259 # Number of branches executed
+system.cpu1.iew.EXEC:nop 45275 # number of nop insts executed
+system.cpu1.iew.EXEC:rate 1.310923 # Inst execution rate
+system.cpu1.iew.EXEC:refs 132378 # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores 42378 # Number of stores executed
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu1.iew.WB:consumers 152450 # num instructions consuming a value
-system.cpu1.iew.WB:count 262125 # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout 0.975992 # average fanout of values written-back
+system.cpu1.iew.WB:consumers 152453 # num instructions consuming a value
+system.cpu1.iew.WB:count 262146 # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout 0.975993 # average fanout of values written-back
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers 148790 # num instructions producing a value
-system.cpu1.iew.WB:rate 1.309322 # insts written-back per cycle
-system.cpu1.iew.WB:sent 262257 # cumulative count of insts sent to commit
+system.cpu1.iew.WB:producers 148793 # num instructions producing a value
+system.cpu1.iew.WB:rate 1.309100 # insts written-back per cycle
+system.cpu1.iew.WB:sent 262278 # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts 1189 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewBlockCycles 1724 # Number of cycles IEW is blocking
-system.cpu1.iew.iewDispLoadInsts 90756 # Number of dispatched load instructions
+system.cpu1.iew.iewBlockCycles 1723 # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts 90759 # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts 936 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts 579 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispStoreInsts 42793 # Number of dispatched store instructions
-system.cpu1.iew.iewDispatchedInsts 311506 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewExecLoadInsts 89997 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 940 # Number of squashed instructions skipped in execute
-system.cpu1.iew.iewExecutedInsts 262490 # Number of executed instructions
+system.cpu1.iew.iewDispStoreInsts 42808 # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts 311533 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts 90000 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 943 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts 262511 # Number of executed instructions
system.cpu1.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.iewSquashCycles 1776 # Number of cycles IEW is squashing
+system.cpu1.iew.iewSquashCycles 1778 # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.memOrderViolation 37 # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads 1508 # Number of loads squashed
-system.cpu1.iew.lsq.thread.0.squashedStores 764 # Number of stores squashed
+system.cpu1.iew.lsq.thread.0.squashedStores 779 # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents 37 # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect 207 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect 982 # Number of branches that were predicted taken incorrectly
-system.cpu1.ipc 1.263867 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.263867 # IPC: Total IPC of All Threads
+system.cpu1.ipc 1.263582 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.263582 # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu 125150 47.51% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead 95884 36.40% 83.91% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite 42396 16.09% 100.00% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntAlu 125153 47.50% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemRead 95890 36.40% 83.90% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemWrite 42411 16.10% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total 263430 # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt 193 # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate 0.000733 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:FU_type_0::total 263454 # Type of FU issued
+system.cpu1.iq.ISSUE:fu_busy_cnt 196 # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu 10 5.18% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.18% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead 55 28.50% 33.68% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite 128 66.32% 100.00% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntAlu 10 5.10% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.10% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemRead 55 28.06% 33.16% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemWrite 131 66.84% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples 196865 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean 1.338125 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.287182 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::samples 196924 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::mean 1.337846 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.287201 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0 78477 39.86% 39.86% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1 26779 13.60% 53.47% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2 44704 22.71% 76.17% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3 42537 21.61% 97.78% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4 2555 1.30% 99.08% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::0 78523 39.87% 39.87% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::1 26788 13.60% 53.48% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::2 44704 22.70% 76.18% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::3 42538 21.60% 97.78% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::4 2558 1.30% 99.08% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5 1568 0.80% 99.88% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6 153 0.08% 99.95% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total 196865 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate 1.315841 # Inst issue rate
-system.cpu1.iq.iqInstsAdded 259216 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqInstsIssued 263430 # Number of instructions issued
-system.cpu1.iq.iqNonSpecInstsAdded 7018 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqSquashedInstsExamined 6568 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.ISSUE:issued_per_cycle::total 196924 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:rate 1.315632 # Inst issue rate
+system.cpu1.iq.iqInstsAdded 259237 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued 263454 # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded 7021 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined 6583 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.iqSquashedOperandsExamined 6183 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.memDep0.conflictingLoads 44382 # Number of conflicting loads.
+system.cpu1.iq.iqSquashedOperandsExamined 6195 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.memDep0.conflictingLoads 44385 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 38318 # Number of conflicting stores.
-system.cpu1.memDep0.insertedLoads 90756 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 42793 # Number of stores inserted to the mem dependence unit.
-system.cpu1.numCycles 200199 # number of cpu cycles simulated
-system.cpu1.rename.RENAME:BlockCycles 7060 # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps 207910 # Number of HB maps that are committed
+system.cpu1.memDep0.insertedLoads 90759 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 42808 # Number of stores inserted to the mem dependence unit.
+system.cpu1.numCycles 200249 # number of cpu cycles simulated
+system.cpu1.rename.RENAME:BlockCycles 7062 # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps 207913 # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents 85 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles 54204 # Number of cycles rename is idle
+system.cpu1.rename.RENAME:IdleCycles 54227 # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents 50 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:RenameLookups 600624 # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts 313715 # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands 216199 # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles 113621 # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles 1776 # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:RenameLookups 600696 # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts 313742 # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands 216202 # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles 113632 # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles 1778 # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles 643 # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps 8289 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:serializeStallCycles 12945 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializeStallCycles 12952 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts 960 # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts 2963 # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts 1012 # count of temporary serializing insts renamed
system.cpu1.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.BTBHits 47889 # Number of BTB hits
-system.cpu2.BPredUnit.BTBLookups 50081 # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits 47901 # Number of BTB hits
+system.cpu2.BPredUnit.BTBLookups 50093 # Number of BTB lookups
system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu2.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.condPredicted 50180 # Number of conditional branches predicted
-system.cpu2.BPredUnit.lookups 50180 # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted 50192 # Number of conditional branches predicted
+system.cpu2.BPredUnit.lookups 50192 # Number of BP lookups
system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu2.commit.COM:branches 47494 # Number of branches committed
+system.cpu2.commit.COM:branches 47506 # Number of branches committed
system.cpu2.commit.COM:bw_lim_events 498 # number cycles where commit BW limit reached
system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.commit.COM:committed_per_cycle::samples 185767 # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::mean 1.418212 # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::stdev 1.887646 # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::samples 185809 # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::mean 1.418279 # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::stdev 1.887696 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::0 86596 46.62% 46.62% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::1 48193 25.94% 72.56% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::0 86613 46.61% 46.61% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::1 48206 25.94% 72.56% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::2 7461 4.02% 76.57% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::3 8520 4.59% 81.16% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::4 2452 1.32% 82.48% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::5 31422 16.91% 99.40% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::4 2453 1.32% 82.48% # Number of insts commited each cycle
+system.cpu2.commit.COM:committed_per_cycle::5 31433 16.92% 99.40% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::6 495 0.27% 99.66% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::7 130 0.07% 99.73% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::8 498 0.27% 100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::total 185767 # Number of insts commited each cycle
-system.cpu2.commit.COM:count 263457 # Number of instructions committed
-system.cpu2.commit.COM:loads 75571 # Number of loads committed
+system.cpu2.commit.COM:committed_per_cycle::total 185809 # Number of insts commited each cycle
+system.cpu2.commit.COM:count 263529 # Number of instructions committed
+system.cpu2.commit.COM:loads 75595 # Number of loads committed
system.cpu2.commit.COM:membars 6984 # Number of memory barriers committed
-system.cpu2.commit.COM:refs 110122 # Number of memory references committed
+system.cpu2.commit.COM:refs 110158 # Number of memory references committed
system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.branchMispredicts 1085 # The number of times a branch was mispredicted
-system.cpu2.commit.commitCommittedInsts 263457 # The number of committed instructions
+system.cpu2.commit.commitCommittedInsts 263529 # The number of committed instructions
system.cpu2.commit.commitNonSpecStalls 7697 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.commitSquashedInsts 7870 # The number of squashed insts skipped by commit
-system.cpu2.committedInsts 218188 # Number of Instructions Simulated
-system.cpu2.committedInsts_total 218188 # Number of Instructions Simulated
-system.cpu2.cpi 0.916214 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.916214 # CPI: Total CPI of All Threads
-system.cpu2.dcache.ReadReq_accesses 45603 # number of ReadReq accesses(hits+misses)
+system.cpu2.commit.commitSquashedInsts 7885 # The number of squashed insts skipped by commit
+system.cpu2.committedInsts 218248 # Number of Instructions Simulated
+system.cpu2.committedInsts_total 218248 # Number of Instructions Simulated
+system.cpu2.cpi 0.916192 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.916192 # CPI: Total CPI of All Threads
+system.cpu2.dcache.ReadReq_accesses 45615 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 22462.882096 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 15906.060606 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_hits 45145 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits 45157 # number of ReadReq hits
system.cpu2.dcache.ReadReq_miss_latency 10288000 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_rate 0.010043 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate 0.010041 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses 458 # number of ReadReq misses
system.cpu2.dcache.ReadReq_mshr_hits 293 # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_miss_latency 2624500 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003618 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003617 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses
system.cpu2.dcache.SwapReq_accesses 67 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_avg_miss_latency 27057.692308 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_mshr_miss_latency 1251000 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_rate 0.776119 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses
-system.cpu2.dcache.WriteReq_accesses 34484 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_avg_miss_latency 24804.878049 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_accesses 34496 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_avg_miss_latency 24833.333333 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16634.615385 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_hits 34361 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_latency 3051000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_rate 0.003567 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_hits 34373 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_miss_latency 3054500 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_rate 0.003566 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_misses 123 # number of WriteReq misses
system.cpu2.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_miss_latency 1730000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_rate 0.003016 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate 0.003015 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_misses 104 # number of WriteReq MSHR misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_refs 1342.733333 # Average number of references to valid blocks.
+system.cpu2.dcache.avg_refs 1343.133333 # Average number of references to valid blocks.
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.demand_accesses 80087 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_avg_miss_latency 22958.691910 # average overall miss latency
+system.cpu2.dcache.demand_accesses 80111 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_avg_miss_latency 22964.716007 # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency 16187.732342 # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 79506 # number of demand (read+write) hits
-system.cpu2.dcache.demand_miss_latency 13339000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.007255 # miss rate for demand accesses
+system.cpu2.dcache.demand_hits 79530 # number of demand (read+write) hits
+system.cpu2.dcache.demand_miss_latency 13342500 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_rate 0.007252 # miss rate for demand accesses
system.cpu2.dcache.demand_misses 581 # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits 312 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency 4354500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_rate 0.003359 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate 0.003358 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0 0.052876 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_%::1 -0.017040 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_blocks::0 27.072320 # Average occupied blocks per context
-system.cpu2.dcache.occ_blocks::1 -8.724259 # Average occupied blocks per context
-system.cpu2.dcache.overall_accesses 80087 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_avg_miss_latency 22958.691910 # average overall miss latency
+system.cpu2.dcache.occ_%::0 0.052845 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_%::1 -0.017028 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_blocks::0 27.056623 # Average occupied blocks per context
+system.cpu2.dcache.occ_blocks::1 -8.718285 # Average occupied blocks per context
+system.cpu2.dcache.overall_accesses 80111 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_avg_miss_latency 22964.716007 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 16187.732342 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 79506 # number of overall hits
-system.cpu2.dcache.overall_miss_latency 13339000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.007255 # miss rate for overall accesses
+system.cpu2.dcache.overall_hits 79530 # number of overall hits
+system.cpu2.dcache.overall_miss_latency 13342500 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_rate 0.007252 # miss rate for overall accesses
system.cpu2.dcache.overall_misses 581 # number of overall misses
system.cpu2.dcache.overall_mshr_hits 312 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency 4354500 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_rate 0.003359 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate 0.003358 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_misses 269 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.dcache.replacements 2 # number of replacements
system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.dcache.tagsinuse 18.348061 # Cycle average of tags in use
-system.cpu2.dcache.total_refs 40282 # Total number of references to valid blocks.
+system.cpu2.dcache.tagsinuse 18.338338 # Cycle average of tags in use
+system.cpu2.dcache.total_refs 40294 # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks 1 # number of writebacks
-system.cpu2.decode.DECODE:BlockedCycles 22115 # Number of cycles decode is blocked
-system.cpu2.decode.DECODE:DecodedInsts 275229 # Number of instructions handled by decode
-system.cpu2.decode.DECODE:IdleCycles 60651 # Number of cycles decode is idle
-system.cpu2.decode.DECODE:RunCycles 96513 # Number of cycles decode is running
-system.cpu2.decode.DECODE:SquashCycles 1718 # Number of cycles decode is squashing
+system.cpu2.decode.DECODE:BlockedCycles 22122 # Number of cycles decode is blocked
+system.cpu2.decode.DECODE:DecodedInsts 275316 # Number of instructions handled by decode
+system.cpu2.decode.DECODE:IdleCycles 60659 # Number of cycles decode is idle
+system.cpu2.decode.DECODE:RunCycles 96539 # Number of cycles decode is running
+system.cpu2.decode.DECODE:SquashCycles 1720 # Number of cycles decode is squashing
system.cpu2.decode.DECODE:UnblockCycles 6488 # Number of cycles decode is unblocking
-system.cpu2.fetch.Branches 50180 # Number of branches that fetch encountered
-system.cpu2.fetch.CacheLines 22951 # Number of cache lines fetched
-system.cpu2.fetch.Cycles 126346 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.Insts 276356 # Number of instructions fetch has processed
-system.cpu2.fetch.SquashCycles 1162 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.branchRate 0.251017 # Number of branch fetches per cycle
-system.cpu2.fetch.icacheStallCycles 22951 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.predictedBranches 47889 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.rate 1.382423 # Number of inst fetches per cycle
-system.cpu2.fetch.rateDist::samples 194083 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.423906 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 1.970447 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.Branches 50192 # Number of branches that fetch encountered
+system.cpu2.fetch.CacheLines 22953 # Number of cache lines fetched
+system.cpu2.fetch.Cycles 126374 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.IcacheSquashes 220 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.Insts 276443 # Number of instructions fetch has processed
+system.cpu2.fetch.SquashCycles 1163 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.branchRate 0.251014 # Number of branch fetches per cycle
+system.cpu2.fetch.icacheStallCycles 22953 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.predictedBranches 47901 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.rate 1.382512 # Number of inst fetches per cycle
+system.cpu2.fetch.rateDist::samples 194140 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.423936 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 1.970541 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 90718 46.74% 46.74% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 54044 27.85% 74.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 90749 46.74% 46.74% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 54056 27.84% 74.59% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 8214 4.23% 78.82% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 2581 1.33% 80.15% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 1900 0.98% 81.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 32424 16.71% 97.83% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 32436 16.71% 97.83% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 2464 1.27% 99.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 267 0.14% 99.24% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1471 0.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 268 0.14% 99.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1472 0.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 194083 # Number of instructions fetched each cycle (Total)
-system.cpu2.icache.ReadReq_accesses 22951 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_avg_miss_latency 21668.711656 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18378.959276 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_hits 22462 # number of ReadReq hits
-system.cpu2.icache.ReadReq_miss_latency 10596000 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_rate 0.021306 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_misses 489 # number of ReadReq misses
-system.cpu2.icache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_miss_latency 8123500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate 0.019258 # mshr miss rate for ReadReq accesses
+system.cpu2.fetch.rateDist::total 194140 # Number of instructions fetched each cycle (Total)
+system.cpu2.icache.ReadReq_accesses 22953 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_avg_miss_latency 21650 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18383.484163 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_hits 22463 # number of ReadReq hits
+system.cpu2.icache.ReadReq_miss_latency 10608500 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_rate 0.021348 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_misses 490 # number of ReadReq misses
+system.cpu2.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_miss_latency 8125500 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate 0.019257 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_misses 442 # number of ReadReq MSHR misses
system.cpu2.icache.avg_blocked_cycles::no_mshrs 18250 # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_refs 50.819005 # Average number of references to valid blocks.
+system.cpu2.icache.avg_refs 50.821267 # Average number of references to valid blocks.
system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_mshrs 36500 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.demand_accesses 22951 # number of demand (read+write) accesses
-system.cpu2.icache.demand_avg_miss_latency 21668.711656 # average overall miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 18378.959276 # average overall mshr miss latency
-system.cpu2.icache.demand_hits 22462 # number of demand (read+write) hits
-system.cpu2.icache.demand_miss_latency 10596000 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_rate 0.021306 # miss rate for demand accesses
-system.cpu2.icache.demand_misses 489 # number of demand (read+write) misses
-system.cpu2.icache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_miss_latency 8123500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_rate 0.019258 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_accesses 22953 # number of demand (read+write) accesses
+system.cpu2.icache.demand_avg_miss_latency 21650 # average overall miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency 18383.484163 # average overall mshr miss latency
+system.cpu2.icache.demand_hits 22463 # number of demand (read+write) hits
+system.cpu2.icache.demand_miss_latency 10608500 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_rate 0.021348 # miss rate for demand accesses
+system.cpu2.icache.demand_misses 490 # number of demand (read+write) misses
+system.cpu2.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_miss_latency 8125500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_rate 0.019257 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0 0.176802 # Average percentage of cache occupancy
-system.cpu2.icache.occ_blocks::0 90.522409 # Average occupied blocks per context
-system.cpu2.icache.overall_accesses 22951 # number of overall (read+write) accesses
-system.cpu2.icache.overall_avg_miss_latency 21668.711656 # average overall miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency 18378.959276 # average overall mshr miss latency
+system.cpu2.icache.occ_%::0 0.176697 # Average percentage of cache occupancy
+system.cpu2.icache.occ_blocks::0 90.468971 # Average occupied blocks per context
+system.cpu2.icache.overall_accesses 22953 # number of overall (read+write) accesses
+system.cpu2.icache.overall_avg_miss_latency 21650 # average overall miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency 18383.484163 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.icache.overall_hits 22462 # number of overall hits
-system.cpu2.icache.overall_miss_latency 10596000 # number of overall miss cycles
-system.cpu2.icache.overall_miss_rate 0.021306 # miss rate for overall accesses
-system.cpu2.icache.overall_misses 489 # number of overall misses
-system.cpu2.icache.overall_mshr_hits 47 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_miss_latency 8123500 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_rate 0.019258 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_hits 22463 # number of overall hits
+system.cpu2.icache.overall_miss_latency 10608500 # number of overall miss cycles
+system.cpu2.icache.overall_miss_rate 0.021348 # miss rate for overall accesses
+system.cpu2.icache.overall_misses 490 # number of overall misses
+system.cpu2.icache.overall_mshr_hits 48 # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_miss_latency 8125500 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_rate 0.019257 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_misses 442 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu2.icache.replacements 332 # number of replacements
system.cpu2.icache.sampled_refs 442 # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.icache.tagsinuse 90.522409 # Cycle average of tags in use
-system.cpu2.icache.total_refs 22462 # Total number of references to valid blocks.
+system.cpu2.icache.tagsinuse 90.468971 # Cycle average of tags in use
+system.cpu2.icache.total_refs 22463 # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks 0 # number of writebacks
-system.cpu2.idleCycles 5824 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.iew.EXEC:branches 48041 # Number of branches executed
-system.cpu2.iew.EXEC:nop 38985 # number of nop insts executed
-system.cpu2.iew.EXEC:rate 1.144757 # Inst execution rate
-system.cpu2.iew.EXEC:refs 111164 # number of memory reference insts executed
-system.cpu2.iew.EXEC:stores 34874 # Number of stores executed
+system.cpu2.idleCycles 5817 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.iew.EXEC:branches 48053 # Number of branches executed
+system.cpu2.iew.EXEC:nop 38997 # number of nop insts executed
+system.cpu2.iew.EXEC:rate 1.144831 # Inst execution rate
+system.cpu2.iew.EXEC:refs 111212 # number of memory reference insts executed
+system.cpu2.iew.EXEC:stores 34898 # Number of stores executed
system.cpu2.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu2.iew.WB:consumers 131236 # num instructions consuming a value
-system.cpu2.iew.WB:count 228477 # cumulative count of insts written-back
-system.cpu2.iew.WB:fanout 0.972142 # average fanout of values written-back
+system.cpu2.iew.WB:consumers 131272 # num instructions consuming a value
+system.cpu2.iew.WB:count 228549 # cumulative count of insts written-back
+system.cpu2.iew.WB:fanout 0.972149 # average fanout of values written-back
system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.iew.WB:producers 127580 # num instructions producing a value
-system.cpu2.iew.WB:rate 1.142916 # insts written-back per cycle
-system.cpu2.iew.WB:sent 228606 # cumulative count of insts sent to commit
+system.cpu2.iew.WB:producers 127616 # num instructions producing a value
+system.cpu2.iew.WB:rate 1.142991 # insts written-back per cycle
+system.cpu2.iew.WB:sent 228678 # cumulative count of insts sent to commit
system.cpu2.iew.branchMispredicts 1190 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewBlockCycles 1615 # Number of cycles IEW is blocking
-system.cpu2.iew.iewDispLoadInsts 76990 # Number of dispatched load instructions
+system.cpu2.iew.iewDispLoadInsts 77014 # Number of dispatched load instructions
system.cpu2.iew.iewDispNonSpecInsts 921 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewDispSquashedInsts 577 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispStoreInsts 35262 # Number of dispatched store instructions
-system.cpu2.iew.iewDispatchedInsts 271358 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewExecLoadInsts 76290 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 955 # Number of squashed instructions skipped in execute
-system.cpu2.iew.iewExecutedInsts 228845 # Number of executed instructions
+system.cpu2.iew.iewDispStoreInsts 35289 # Number of dispatched store instructions
+system.cpu2.iew.iewDispatchedInsts 271445 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewExecLoadInsts 76314 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 958 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewExecutedInsts 228917 # Number of executed instructions
system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.iewSquashCycles 1718 # Number of cycles IEW is squashing
+system.cpu2.iew.iewSquashCycles 1720 # Number of cycles IEW is squashing
system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.lsq.thread.0.forwLoads 30669 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread.0.forwLoads 30681 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread.0.memOrderViolation 36 # Number of memory ordering violations
system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread.0.squashedLoads 1419 # Number of loads squashed
-system.cpu2.iew.lsq.thread.0.squashedStores 711 # Number of stores squashed
+system.cpu2.iew.lsq.thread.0.squashedStores 726 # Number of stores squashed
system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations
system.cpu2.iew.predictedNotTakenIncorrect 197 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.predictedTakenIncorrect 993 # Number of branches that were predicted taken incorrectly
-system.cpu2.ipc 1.091448 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.091448 # IPC: Total IPC of All Threads
+system.cpu2.ipc 1.091475 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.091475 # IPC: Total IPC of All Threads
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntAlu 111446 48.50% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.50% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::MemRead 83455 36.32% 84.81% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::MemWrite 34899 15.19% 100.00% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::IntAlu 111470 48.49% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.49% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::MemRead 83479 36.31% 84.81% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::MemWrite 34926 15.19% 100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::total 229800 # Type of FU issued
-system.cpu2.iq.ISSUE:fu_busy_cnt 187 # FU busy when requested
-system.cpu2.iq.ISSUE:fu_busy_rate 0.000814 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.ISSUE:FU_type_0::total 229875 # Type of FU issued
+system.cpu2.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested
+system.cpu2.iq.ISSUE:fu_busy_rate 0.000827 # FU busy rate (busy events/executed inst)
system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntAlu 11 5.88% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::MemRead 48 25.67% 31.55% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::MemWrite 128 68.45% 100.00% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::IntAlu 11 5.79% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.79% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::MemRead 48 25.26% 31.05% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::MemWrite 131 68.95% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:issued_per_cycle::samples 194083 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::mean 1.184030 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::stdev 1.270781 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::samples 194140 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::mean 1.184068 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::stdev 1.270828 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::0 86865 44.76% 44.76% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::1 30647 15.79% 60.55% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::2 37170 19.15% 79.70% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::3 34973 18.02% 97.72% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::4 2604 1.34% 99.06% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::0 86894 44.76% 44.76% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::1 30647 15.79% 60.54% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::2 37182 19.15% 79.70% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::3 34986 18.02% 97.72% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::4 2607 1.34% 99.06% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::5 1569 0.81% 99.87% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::6 161 0.08% 99.95% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::7 85 0.04% 100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::total 194083 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:rate 1.149535 # Inst issue rate
-system.cpu2.iq.iqInstsAdded 224135 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqInstsIssued 229800 # Number of instructions issued
+system.cpu2.iq.ISSUE:issued_per_cycle::total 194140 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:rate 1.149622 # Inst issue rate
+system.cpu2.iq.iqInstsAdded 224210 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqInstsIssued 229875 # Number of instructions issued
system.cpu2.iq.iqNonSpecInstsAdded 8238 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqSquashedInstsExamined 6304 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedInstsExamined 6319 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedNonSpecRemoved 541 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.iqSquashedOperandsExamined 5829 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.memDep0.conflictingLoads 38114 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 30803 # Number of conflicting stores.
-system.cpu2.memDep0.insertedLoads 76990 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 35262 # Number of stores inserted to the mem dependence unit.
-system.cpu2.numCycles 199907 # number of cpu cycles simulated
+system.cpu2.iq.iqSquashedOperandsExamined 5841 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.memDep0.conflictingLoads 38126 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 30815 # Number of conflicting stores.
+system.cpu2.memDep0.insertedLoads 77014 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 35289 # Number of stores inserted to the mem dependence unit.
+system.cpu2.numCycles 199957 # number of cpu cycles simulated
system.cpu2.rename.RENAME:BlockCycles 8148 # Number of cycles rename is blocking
-system.cpu2.rename.RENAME:CommittedMaps 179272 # Number of HB maps that are committed
+system.cpu2.rename.RENAME:CommittedMaps 179320 # Number of HB maps that are committed
system.cpu2.rename.RENAME:IQFullEvents 31 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.RENAME:IdleCycles 61263 # Number of cycles rename is idle
+system.cpu2.rename.RENAME:IdleCycles 61271 # Number of cycles rename is idle
system.cpu2.rename.RENAME:LSQFullEvents 56 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RENAME:RenameLookups 515407 # Number of register rename lookups that rename has made
-system.cpu2.rename.RENAME:RenamedInsts 273547 # Number of instructions processed by rename
-system.cpu2.rename.RENAME:RenamedOperands 187363 # Number of destination operands rename has renamed
-system.cpu2.rename.RENAME:RunCycles 102562 # Number of cycles rename is running
-system.cpu2.rename.RENAME:SquashCycles 1718 # Number of cycles rename is squashing
+system.cpu2.rename.RENAME:RenameLookups 515611 # Number of register rename lookups that rename has made
+system.cpu2.rename.RENAME:RenamedInsts 273634 # Number of instructions processed by rename
+system.cpu2.rename.RENAME:RenamedOperands 187411 # Number of destination operands rename has renamed
+system.cpu2.rename.RENAME:RunCycles 102588 # Number of cycles rename is running
+system.cpu2.rename.RENAME:SquashCycles 1720 # Number of cycles rename is squashing
system.cpu2.rename.RENAME:UnblockCycles 553 # Number of cycles rename is unblocking
system.cpu2.rename.RENAME:UndoneMaps 8091 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.RENAME:serializeStallCycles 13241 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RENAME:serializeStallCycles 13248 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RENAME:serializingInsts 943 # count of serializing insts renamed
system.cpu2.rename.RENAME:skidInsts 2678 # count of insts added to the skid buffer
system.cpu2.rename.RENAME:tempSerializingInsts 998 # count of temporary serializing insts renamed
system.cpu2.timesIdled 306 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.BTBHits 51000 # Number of BTB hits
-system.cpu3.BPredUnit.BTBLookups 53222 # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits 51008 # Number of BTB hits
+system.cpu3.BPredUnit.BTBLookups 53230 # Number of BTB lookups
system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu3.BPredUnit.condIncorrect 1107 # Number of conditional branches incorrect
-system.cpu3.BPredUnit.condPredicted 53282 # Number of conditional branches predicted
-system.cpu3.BPredUnit.lookups 53282 # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted 53290 # Number of conditional branches predicted
+system.cpu3.BPredUnit.lookups 53290 # Number of BP lookups
system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu3.commit.COM:branches 50377 # Number of branches committed
+system.cpu3.commit.COM:branches 50385 # Number of branches committed
system.cpu3.commit.COM:bw_lim_events 486 # number cycles where commit BW limit reached
system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.commit.COM:committed_per_cycle::samples 188057 # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::mean 1.497514 # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::stdev 1.921417 # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::samples 188101 # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::mean 1.497398 # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::stdev 1.921379 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::0 82996 44.13% 44.13% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::1 51194 27.22% 71.36% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::2 7476 3.98% 75.33% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::3 8061 4.29% 79.62% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::4 2450 1.30% 80.92% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::5 34892 18.55% 99.47% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::0 83023 44.14% 44.14% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::1 51203 27.22% 71.36% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::2 7476 3.97% 75.33% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::3 8063 4.29% 79.62% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::4 2451 1.30% 80.92% # Number of insts commited each cycle
+system.cpu3.commit.COM:committed_per_cycle::5 34897 18.55% 99.47% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::6 373 0.20% 99.67% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::total 188057 # Number of insts commited each cycle
-system.cpu3.commit.COM:count 281618 # Number of instructions committed
-system.cpu3.commit.COM:loads 81766 # Number of loads committed
-system.cpu3.commit.COM:membars 6531 # Number of memory barriers committed
-system.cpu3.commit.COM:refs 119649 # Number of memory references committed
+system.cpu3.commit.COM:committed_per_cycle::total 188101 # Number of insts commited each cycle
+system.cpu3.commit.COM:count 281662 # Number of instructions committed
+system.cpu3.commit.COM:loads 81780 # Number of loads committed
+system.cpu3.commit.COM:membars 6533 # Number of memory barriers committed
+system.cpu3.commit.COM:refs 119669 # Number of memory references committed
system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.branchMispredicts 1107 # The number of times a branch was mispredicted
-system.cpu3.commit.commitCommittedInsts 281618 # The number of committed instructions
-system.cpu3.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.commitSquashedInsts 8574 # The number of squashed insts skipped by commit
-system.cpu3.committedInsts 233925 # Number of Instructions Simulated
-system.cpu3.committedInsts_total 233925 # Number of Instructions Simulated
-system.cpu3.cpi 0.853423 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.853423 # CPI: Total CPI of All Threads
-system.cpu3.dcache.ReadReq_accesses 48473 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_avg_miss_latency 22753.504673 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14018.518519 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_hits 48045 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_miss_latency 9738500 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_rate 0.008830 # miss rate for ReadReq accesses
+system.cpu3.commit.commitCommittedInsts 281662 # The number of committed instructions
+system.cpu3.commit.commitNonSpecStalls 7252 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.commitSquashedInsts 8589 # The number of squashed insts skipped by commit
+system.cpu3.committedInsts 233959 # Number of Instructions Simulated
+system.cpu3.committedInsts_total 233959 # Number of Instructions Simulated
+system.cpu3.cpi 0.853513 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 0.853513 # CPI: Total CPI of All Threads
+system.cpu3.dcache.ReadReq_accesses 48481 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_avg_miss_latency 22746.495327 # average ReadReq miss latency
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+system.cpu3.dcache.ReadReq_hits 48053 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_miss_latency 9735500 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_rate 0.008828 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses 428 # number of ReadReq misses
system.cpu3.dcache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_miss_latency 2271000 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency 2268000 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.003342 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses
system.cpu3.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_mshr_miss_latency 1330000 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_rate 0.821918 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_misses 60 # number of SwapReq MSHR misses
-system.cpu3.dcache.WriteReq_accesses 37810 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_avg_miss_latency 24109.243697 # average WriteReq miss latency
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+system.cpu3.dcache.WriteReq_avg_miss_latency 24138.655462 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15764.705882 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_hits 37691 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_latency 2869000 # number of WriteReq miss cycles
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system.cpu3.dcache.WriteReq_miss_rate 0.003147 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_misses 119 # number of WriteReq misses
system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_miss_latency 1608000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002698 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002697 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_refs 1503.344828 # Average number of references to valid blocks.
+system.cpu3.dcache.avg_refs 1503.551724 # Average number of references to valid blocks.
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.demand_accesses 86283 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_avg_miss_latency 23048.446069 # average overall miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency 14693.181818 # average overall mshr miss latency
-system.cpu3.dcache.demand_hits 85736 # number of demand (read+write) hits
-system.cpu3.dcache.demand_miss_latency 12607500 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_rate 0.006340 # miss rate for demand accesses
+system.cpu3.dcache.demand_accesses 86297 # number of demand (read+write) accesses
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system.cpu3.dcache.demand_misses 547 # number of demand (read+write) misses
system.cpu3.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_miss_latency 3879000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_rate 0.003060 # mshr miss rate for demand accesses
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system.cpu3.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.dcache.occ_%::1 -0.015422 # Average percentage of cache occupancy
-system.cpu3.dcache.occ_blocks::0 25.223945 # Average occupied blocks per context
-system.cpu3.dcache.occ_blocks::1 -7.896204 # Average occupied blocks per context
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-system.cpu3.dcache.overall_avg_miss_latency 23048.446069 # average overall miss latency
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+system.cpu3.dcache.occ_%::1 -0.015412 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_blocks::0 25.208240 # Average occupied blocks per context
+system.cpu3.dcache.occ_blocks::1 -7.890970 # Average occupied blocks per context
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+system.cpu3.dcache.overall_avg_miss_latency 23049.360146 # average overall miss latency
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system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.dcache.overall_hits 85736 # number of overall hits
-system.cpu3.dcache.overall_miss_latency 12607500 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_rate 0.006340 # miss rate for overall accesses
+system.cpu3.dcache.overall_hits 85750 # number of overall hits
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+system.cpu3.dcache.overall_miss_rate 0.006339 # miss rate for overall accesses
system.cpu3.dcache.overall_misses 547 # number of overall misses
system.cpu3.dcache.overall_mshr_hits 283 # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_miss_latency 3879000 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_rate 0.003060 # mshr miss rate for overall accesses
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system.cpu3.dcache.overall_mshr_misses 264 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.dcache.replacements 2 # number of replacements
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.dcache.tagsinuse 17.327741 # Cycle average of tags in use
-system.cpu3.dcache.total_refs 43597 # Total number of references to valid blocks.
+system.cpu3.dcache.tagsinuse 17.317269 # Cycle average of tags in use
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system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks 1 # number of writebacks
-system.cpu3.decode.DECODE:BlockedCycles 21716 # Number of cycles decode is blocked
-system.cpu3.decode.DECODE:DecodedInsts 294261 # Number of instructions handled by decode
-system.cpu3.decode.DECODE:IdleCycles 57777 # Number of cycles decode is idle
-system.cpu3.decode.DECODE:RunCycles 102518 # Number of cycles decode is running
-system.cpu3.decode.DECODE:SquashCycles 1820 # Number of cycles decode is squashing
-system.cpu3.decode.DECODE:UnblockCycles 6046 # Number of cycles decode is unblocking
-system.cpu3.fetch.Branches 53282 # Number of branches that fetch encountered
-system.cpu3.fetch.CacheLines 21872 # Number of cache lines fetched
-system.cpu3.fetch.Cycles 130835 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.IcacheSquashes 221 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.Insts 295412 # Number of instructions fetch has processed
-system.cpu3.fetch.SquashCycles 1181 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.branchRate 0.266894 # Number of branch fetches per cycle
-system.cpu3.fetch.icacheStallCycles 21872 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.predictedBranches 51000 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.rate 1.479746 # Number of inst fetches per cycle
-system.cpu3.fetch.rateDist::samples 196481 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.503514 # Number of instructions fetched each cycle (Total)
+system.cpu3.decode.DECODE:BlockedCycles 21721 # Number of cycles decode is blocked
+system.cpu3.decode.DECODE:DecodedInsts 294320 # Number of instructions handled by decode
+system.cpu3.decode.DECODE:IdleCycles 57795 # Number of cycles decode is idle
+system.cpu3.decode.DECODE:RunCycles 102536 # Number of cycles decode is running
+system.cpu3.decode.DECODE:SquashCycles 1822 # Number of cycles decode is squashing
+system.cpu3.decode.DECODE:UnblockCycles 6048 # Number of cycles decode is unblocking
+system.cpu3.fetch.Branches 53290 # Number of branches that fetch encountered
+system.cpu3.fetch.CacheLines 21878 # Number of cache lines fetched
+system.cpu3.fetch.Cycles 130861 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.IcacheSquashes 222 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.Insts 295471 # Number of instructions fetch has processed
+system.cpu3.fetch.SquashCycles 1182 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.branchRate 0.266868 # Number of branch fetches per cycle
+system.cpu3.fetch.icacheStallCycles 21878 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.predictedBranches 51008 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.rate 1.479671 # Number of inst fetches per cycle
+system.cpu3.fetch.rateDist::samples 196540 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.503363 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.005027 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 87542 44.55% 44.55% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 56519 28.77% 73.32% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 7661 3.90% 77.22% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 87581 44.56% 44.56% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 56529 28.76% 73.32% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 7663 3.90% 77.22% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 2862 1.46% 78.68% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 1914 0.97% 79.65% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 35774 18.21% 97.86% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 35780 18.20% 97.86% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 2478 1.26% 99.12% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 257 0.13% 99.25% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 1474 0.75% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 258 0.13% 99.25% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 1475 0.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 196481 # Number of instructions fetched each cycle (Total)
-system.cpu3.icache.ReadReq_accesses 21872 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_avg_miss_latency 14323.590814 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11652.370203 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_hits 21393 # number of ReadReq hits
-system.cpu3.icache.ReadReq_miss_latency 6861000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_rate 0.021900 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_misses 479 # number of ReadReq misses
-system.cpu3.icache.ReadReq_mshr_hits 36 # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_miss_latency 5162000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate 0.020254 # mshr miss rate for ReadReq accesses
+system.cpu3.fetch.rateDist::total 196540 # Number of instructions fetched each cycle (Total)
+system.cpu3.icache.ReadReq_accesses 21878 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_avg_miss_latency 14319.791667 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11656.884876 # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_hits 21398 # number of ReadReq hits
+system.cpu3.icache.ReadReq_miss_latency 6873500 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_rate 0.021940 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_misses 480 # number of ReadReq misses
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+system.cpu3.icache.ReadReq_mshr_miss_rate 0.020249 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_misses 443 # number of ReadReq MSHR misses
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_refs 48.291196 # Average number of references to valid blocks.
+system.cpu3.icache.avg_refs 48.302483 # Average number of references to valid blocks.
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.demand_accesses 21872 # number of demand (read+write) accesses
-system.cpu3.icache.demand_avg_miss_latency 14323.590814 # average overall miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 11652.370203 # average overall mshr miss latency
-system.cpu3.icache.demand_hits 21393 # number of demand (read+write) hits
-system.cpu3.icache.demand_miss_latency 6861000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_rate 0.021900 # miss rate for demand accesses
-system.cpu3.icache.demand_misses 479 # number of demand (read+write) misses
-system.cpu3.icache.demand_mshr_hits 36 # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_miss_latency 5162000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_rate 0.020254 # mshr miss rate for demand accesses
+system.cpu3.icache.demand_accesses 21878 # number of demand (read+write) accesses
+system.cpu3.icache.demand_avg_miss_latency 14319.791667 # average overall miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency 11656.884876 # average overall mshr miss latency
+system.cpu3.icache.demand_hits 21398 # number of demand (read+write) hits
+system.cpu3.icache.demand_miss_latency 6873500 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_rate 0.021940 # miss rate for demand accesses
+system.cpu3.icache.demand_misses 480 # number of demand (read+write) misses
+system.cpu3.icache.demand_mshr_hits 37 # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_miss_latency 5164000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_rate 0.020249 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0 0.173082 # Average percentage of cache occupancy
-system.cpu3.icache.occ_blocks::0 88.617750 # Average occupied blocks per context
-system.cpu3.icache.overall_accesses 21872 # number of overall (read+write) accesses
-system.cpu3.icache.overall_avg_miss_latency 14323.590814 # average overall miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 11652.370203 # average overall mshr miss latency
+system.cpu3.icache.occ_%::0 0.172972 # Average percentage of cache occupancy
+system.cpu3.icache.occ_blocks::0 88.561786 # Average occupied blocks per context
+system.cpu3.icache.overall_accesses 21878 # number of overall (read+write) accesses
+system.cpu3.icache.overall_avg_miss_latency 14319.791667 # average overall miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency 11656.884876 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.icache.overall_hits 21393 # number of overall hits
-system.cpu3.icache.overall_miss_latency 6861000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_rate 0.021900 # miss rate for overall accesses
-system.cpu3.icache.overall_misses 479 # number of overall misses
-system.cpu3.icache.overall_mshr_hits 36 # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_miss_latency 5162000 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_rate 0.020254 # mshr miss rate for overall accesses
+system.cpu3.icache.overall_hits 21398 # number of overall hits
+system.cpu3.icache.overall_miss_latency 6873500 # number of overall miss cycles
+system.cpu3.icache.overall_miss_rate 0.021940 # miss rate for overall accesses
+system.cpu3.icache.overall_misses 480 # number of overall misses
+system.cpu3.icache.overall_mshr_hits 37 # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_miss_latency 5164000 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_rate 0.020249 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_misses 443 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu3.icache.replacements 331 # number of replacements
system.cpu3.icache.sampled_refs 443 # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 88.617750 # Cycle average of tags in use
-system.cpu3.icache.total_refs 21393 # Total number of references to valid blocks.
+system.cpu3.icache.tagsinuse 88.561786 # Cycle average of tags in use
+system.cpu3.icache.total_refs 21398 # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks 0 # number of writebacks
-system.cpu3.idleCycles 3156 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.iew.EXEC:branches 50931 # Number of branches executed
-system.cpu3.iew.EXEC:nop 42039 # number of nop insts executed
-system.cpu3.iew.EXEC:rate 1.222935 # Inst execution rate
-system.cpu3.iew.EXEC:refs 120716 # number of memory reference insts executed
-system.cpu3.iew.EXEC:stores 38219 # Number of stores executed
+system.cpu3.idleCycles 3147 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.iew.EXEC:branches 50939 # Number of branches executed
+system.cpu3.iew.EXEC:nop 42047 # number of nop insts executed
+system.cpu3.iew.EXEC:rate 1.222869 # Inst execution rate
+system.cpu3.iew.EXEC:refs 120748 # number of memory reference insts executed
+system.cpu3.iew.EXEC:stores 38237 # Number of stores executed
system.cpu3.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu3.iew.WB:consumers 140772 # num instructions consuming a value
-system.cpu3.iew.WB:count 243777 # cumulative count of insts written-back
-system.cpu3.iew.WB:fanout 0.974072 # average fanout of values written-back
+system.cpu3.iew.WB:consumers 140792 # num instructions consuming a value
+system.cpu3.iew.WB:count 243825 # cumulative count of insts written-back
+system.cpu3.iew.WB:fanout 0.974075 # average fanout of values written-back
system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.iew.WB:producers 137122 # num instructions producing a value
-system.cpu3.iew.WB:rate 1.221101 # insts written-back per cycle
-system.cpu3.iew.WB:sent 243910 # cumulative count of insts sent to commit
+system.cpu3.iew.WB:producers 137142 # num instructions producing a value
+system.cpu3.iew.WB:rate 1.221036 # insts written-back per cycle
+system.cpu3.iew.WB:sent 243958 # cumulative count of insts sent to commit
system.cpu3.iew.branchMispredicts 1214 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewBlockCycles 1676 # Number of cycles IEW is blocking
-system.cpu3.iew.iewDispLoadInsts 83353 # Number of dispatched load instructions
+system.cpu3.iew.iewBlockCycles 1672 # Number of cycles IEW is blocking
+system.cpu3.iew.iewDispLoadInsts 83367 # Number of dispatched load instructions
system.cpu3.iew.iewDispNonSpecInsts 943 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewDispSquashedInsts 577 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispStoreInsts 38642 # Number of dispatched store instructions
-system.cpu3.iew.iewDispatchedInsts 290221 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewExecLoadInsts 82497 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 962 # Number of squashed instructions skipped in execute
-system.cpu3.iew.iewExecutedInsts 244143 # Number of executed instructions
+system.cpu3.iew.iewDispStoreInsts 38663 # Number of dispatched store instructions
+system.cpu3.iew.iewDispatchedInsts 290280 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewExecLoadInsts 82511 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 965 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewExecutedInsts 244191 # Number of executed instructions
system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.iewSquashCycles 1820 # Number of cycles IEW is squashing
+system.cpu3.iew.iewSquashCycles 1822 # Number of cycles IEW is squashing
system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking
system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu3.iew.lsq.thread.0.forwLoads 34006 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread.0.forwLoads 34012 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread.0.memOrderViolation 33 # Number of memory ordering violations
system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread.0.squashedLoads 1587 # Number of loads squashed
-system.cpu3.iew.lsq.thread.0.squashedStores 759 # Number of stores squashed
+system.cpu3.iew.lsq.thread.0.squashedStores 774 # Number of stores squashed
system.cpu3.iew.memOrderViolationEvents 33 # Number of memory order violations
system.cpu3.iew.predictedNotTakenIncorrect 191 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.predictedTakenIncorrect 1023 # Number of branches that were predicted taken incorrectly
-system.cpu3.ipc 1.171752 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.171752 # IPC: Total IPC of All Threads
+system.cpu3.ipc 1.171629 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 1.171629 # IPC: Total IPC of All Threads
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntAlu 117646 48.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::MemRead 89212 36.40% 84.40% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::MemWrite 38247 15.60% 100.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::IntAlu 117660 47.99% 47.99% # Type of FU issued
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+system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.99% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.99% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.99% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.99% # Type of FU issued
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+system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.99% # Type of FU issued
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+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.99% # Type of FU issued
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+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.99% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::MemRead 89228 36.40% 84.39% # Type of FU issued
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system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::total 245105 # Type of FU issued
-system.cpu3.iq.ISSUE:fu_busy_cnt 192 # FU busy when requested
-system.cpu3.iq.ISSUE:fu_busy_rate 0.000783 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.ISSUE:FU_type_0::total 245156 # Type of FU issued
+system.cpu3.iq.ISSUE:fu_busy_cnt 195 # FU busy when requested
+system.cpu3.iq.ISSUE:fu_busy_rate 0.000795 # FU busy rate (busy events/executed inst)
system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IntAlu 10 5.21% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.21% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::MemRead 54 28.12% 33.33% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::MemWrite 128 66.67% 100.00% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::IntAlu 10 5.13% 5.13% # attempts to use FU when none available
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+system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.13% # attempts to use FU when none available
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+system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.13% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.13% # attempts to use FU when none available
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+system.cpu3.iq.ISSUE:fu_full::MemWrite 131 67.18% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:issued_per_cycle::samples 196481 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::mean 1.247474 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::stdev 1.278014 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::samples 196540 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::mean 1.247359 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::stdev 1.278033 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::0 83915 42.71% 42.71% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::1 29209 14.87% 57.58% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::2 40640 20.68% 78.26% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::3 38393 19.54% 97.80% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::4 2530 1.29% 99.09% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::0 83952 42.71% 42.71% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::1 29215 14.86% 57.58% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::2 40646 20.68% 78.26% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::3 38400 19.54% 97.80% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::4 2533 1.29% 99.09% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::5 1549 0.79% 99.88% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::6 153 0.08% 99.95% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::7 82 0.04% 99.99% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::total 196481 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:rate 1.227753 # Inst issue rate
-system.cpu3.iq.iqInstsAdded 240238 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqInstsIssued 245105 # Number of instructions issued
-system.cpu3.iq.iqNonSpecInstsAdded 7944 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqSquashedInstsExamined 6797 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.ISSUE:issued_per_cycle::total 196540 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:rate 1.227701 # Inst issue rate
+system.cpu3.iq.iqInstsAdded 240287 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqInstsIssued 245156 # Number of instructions issued
+system.cpu3.iq.iqNonSpecInstsAdded 7946 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqSquashedInstsExamined 6812 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.iqSquashedOperandsExamined 6548 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.memDep0.conflictingLoads 41135 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 34159 # Number of conflicting stores.
-system.cpu3.memDep0.insertedLoads 83353 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 38642 # Number of stores inserted to the mem dependence unit.
-system.cpu3.numCycles 199637 # number of cpu cycles simulated
-system.cpu3.rename.RENAME:BlockCycles 7787 # Number of cycles rename is blocking
-system.cpu3.rename.RENAME:CommittedMaps 192127 # Number of HB maps that are committed
+system.cpu3.iq.iqSquashedOperandsExamined 6560 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.memDep0.conflictingLoads 41143 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 34165 # Number of conflicting stores.
+system.cpu3.memDep0.insertedLoads 83367 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 38663 # Number of stores inserted to the mem dependence unit.
+system.cpu3.numCycles 199687 # number of cpu cycles simulated
+system.cpu3.rename.RENAME:BlockCycles 7785 # Number of cycles rename is blocking
+system.cpu3.rename.RENAME:CommittedMaps 192153 # Number of HB maps that are committed
system.cpu3.rename.RENAME:IQFullEvents 59 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.RENAME:IdleCycles 58403 # Number of cycles rename is idle
+system.cpu3.rename.RENAME:IdleCycles 58421 # Number of cycles rename is idle
system.cpu3.rename.RENAME:LSQFullEvents 39 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RENAME:RenameLookups 554400 # Number of register rename lookups that rename has made
-system.cpu3.rename.RENAME:RenamedInsts 292478 # Number of instructions processed by rename
-system.cpu3.rename.RENAME:RenamedOperands 200449 # Number of destination operands rename has renamed
-system.cpu3.rename.RENAME:RunCycles 108083 # Number of cycles rename is running
-system.cpu3.rename.RENAME:SquashCycles 1820 # Number of cycles rename is squashing
+system.cpu3.rename.RENAME:RenameLookups 554540 # Number of register rename lookups that rename has made
+system.cpu3.rename.RENAME:RenamedInsts 292537 # Number of instructions processed by rename
+system.cpu3.rename.RENAME:RenamedOperands 200475 # Number of destination operands rename has renamed
+system.cpu3.rename.RENAME:RunCycles 108103 # Number of cycles rename is running
+system.cpu3.rename.RENAME:SquashCycles 1822 # Number of cycles rename is squashing
system.cpu3.rename.RENAME:UnblockCycles 588 # Number of cycles rename is unblocking
system.cpu3.rename.RENAME:UndoneMaps 8322 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.RENAME:serializeStallCycles 13196 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RENAME:serializeStallCycles 13203 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RENAME:serializingInsts 964 # count of serializing insts renamed
system.cpu3.rename.RENAME:skidInsts 2784 # count of insts added to the skid buffer
system.cpu3.rename.RENAME:tempSerializingInsts 1016 # count of temporary serializing insts renamed
-system.cpu3.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 73191.489362 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 573333.333333 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 529230.769231 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 573333.333333 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 1749088.925259 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40335.877863 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 6880000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_avg_miss_latency::0 73159.574468 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 573083.333333 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 529000 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::3 573083.333333 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 1748326.241135 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40290.076336 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 6877000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 5284000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5278000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses
system.l2c.ReadReq_accesses::2 456 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3 456 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2060 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 63650.334076 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 2381583.333333 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2 340226.190476 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3 5715800 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 8501259.857885 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::0 63648.106904 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 2381500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2 340214.285714 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3 5715600 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 8500962.392619 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40001.841621 # average ReadReq mshr miss latency
system.l2c.ReadReq_hits::0 240 # number of ReadReq hits
system.l2c.ReadReq_hits::1 447 # number of ReadReq hits
system.l2c.ReadReq_hits::2 372 # number of ReadReq hits
system.l2c.ReadReq_hits::3 451 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1510 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 28579000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency 28578000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.651669 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.026144 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2 0.184211 # miss rate for ReadReq accesses
system.l2c.demand_accesses::2 469 # number of demand (read+write) accesses
system.l2c.demand_accesses::3 468 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2191 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 65302.025783 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 1477458.333333 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 365556.701031 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 2085823.529412 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3994140.589559 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40066.765579 # average overall mshr miss latency
+system.l2c.demand_avg_miss_latency::0 65294.659300 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 1477291.666667 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 365515.463918 # average overall miss latency
+system.l2c.demand_avg_miss_latency::3 2085588.235294 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3993690.025178 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40057.863501 # average overall mshr miss latency
system.l2c.demand_hits::0 240 # number of demand (read+write) hits
system.l2c.demand_hits::1 447 # number of demand (read+write) hits
system.l2c.demand_hits::2 372 # number of demand (read+write) hits
system.l2c.demand_hits::3 451 # number of demand (read+write) hits
system.l2c.demand_hits::total 1510 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 35459000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency 35455000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.693487 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.050955 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 0.206823 # miss rate for demand accesses
system.l2c.demand_misses::3 17 # number of demand (read+write) misses
system.l2c.demand_misses::total 681 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 7 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 27005000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 26999000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0.860792 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 1.430998 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 1.437100 # mshr miss rate for demand accesses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.005563 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.000142 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.000963 # Average percentage of cache occupancy
+system.l2c.occ_%::0 0.005562 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.000141 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.000962 # Average percentage of cache occupancy
system.l2c.occ_%::3 0.000050 # Average percentage of cache occupancy
system.l2c.occ_%::4 0.000078 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 364.605872 # Average occupied blocks per context
-system.l2c.occ_blocks::1 9.278582 # Average occupied blocks per context
-system.l2c.occ_blocks::2 63.097749 # Average occupied blocks per context
-system.l2c.occ_blocks::3 3.264789 # Average occupied blocks per context
-system.l2c.occ_blocks::4 5.109725 # Average occupied blocks per context
+system.l2c.occ_blocks::0 364.482094 # Average occupied blocks per context
+system.l2c.occ_blocks::1 9.273148 # Average occupied blocks per context
+system.l2c.occ_blocks::2 63.060647 # Average occupied blocks per context
+system.l2c.occ_blocks::3 3.262767 # Average occupied blocks per context
+system.l2c.occ_blocks::4 5.106132 # Average occupied blocks per context
system.l2c.overall_accesses::0 783 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 471 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 469 # number of overall (read+write) accesses
system.l2c.overall_accesses::3 468 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2191 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 65302.025783 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 1477458.333333 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 365556.701031 # average overall miss latency
-system.l2c.overall_avg_miss_latency::3 2085823.529412 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 3994140.589559 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40066.765579 # average overall mshr miss latency
+system.l2c.overall_avg_miss_latency::0 65294.659300 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 1477291.666667 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 365515.463918 # average overall miss latency
+system.l2c.overall_avg_miss_latency::3 2085588.235294 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 3993690.025178 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40057.863501 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.l2c.overall_hits::0 240 # number of overall hits
system.l2c.overall_hits::1 447 # number of overall hits
system.l2c.overall_hits::2 372 # number of overall hits
system.l2c.overall_hits::3 451 # number of overall hits
system.l2c.overall_hits::total 1510 # number of overall hits
-system.l2c.overall_miss_latency 35459000 # number of overall miss cycles
+system.l2c.overall_miss_latency 35455000 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.693487 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.050955 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 0.206823 # miss rate for overall accesses
system.l2c.overall_misses::3 17 # number of overall misses
system.l2c.overall_misses::total 681 # number of overall misses
system.l2c.overall_mshr_hits 7 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 27005000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 26999000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0.860792 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 1.430998 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 1.437100 # mshr miss rate for overall accesses
system.l2c.replacements 0 # number of replacements
system.l2c.sampled_refs 545 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 445.356717 # Cycle average of tags in use
+system.l2c.tagsinuse 445.184788 # Cycle average of tags in use
system.l2c.total_refs 1507 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
projects / gem5.git / commitdiff