Add write_xaiger into CHANGELOG
authorEddie Hung <eddie@fpgeh.com>
Thu, 27 Jun 2019 02:17:11 +0000 (19:17 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 27 Jun 2019 02:17:11 +0000 (19:17 -0700)
CHANGELOG

index f0154a81e12c22f1ae8c4336c68cd7ce49414067..73115600cd67f4720599a4f843620a280ebd67b5 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "muxcover -dmux=<cost>"
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
+    - Added "write_xaiger" backend
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)