X86: Make instructions that use intseg preserve all 8 bytes of their addresses.

diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
index 924bfcb6ea751cced98ab3d7aa14b6501f64b177..4e3c9b316fd7d8cfa8f1d86c4d223ebca2b059d7 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
@@ -85,22 +85,22 @@ microcode = '''
     def macroop IN_R_I {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=asz
-        ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
+        ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
     };
 
     def macroop IN_R_R {
         zexti t2, regm, 15, dataSize=8
-        ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
+        ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
     };
 
     def macroop OUT_I_R {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=8
-        st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
+        st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
     };
 
     def macroop OUT_R_R {
         zexti t2, reg, 15, dataSize=8
-        st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
+        st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
     };
 '''

diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index f3c867398ff54b9beae192cff32e6d90c1721aad..7f283c8c16b931240a4dfb51fa5cb0e5eaba4371 100644 (file)
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -85,7 +85,7 @@ microcode = '''
 def macroop RDMSR
 {
     ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
-        dataSize=8, addressSize=4
+        dataSize=8, addressSize=8
     mov rax, rax, t2, dataSize=4
     srli t2, t2, 32, dataSize=8
     mov rdx, rdx, t2, dataSize=4
@@ -97,7 +97,7 @@ def macroop WRMSR
     slli t3, rdx, 32, dataSize=8
     or t2, t2, t3, dataSize=8
     st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
-        dataSize=8, addressSize=4
+        dataSize=8, addressSize=8
 };
 
 def macroop RDTSC