i965: Avoid double-negation of immediate values in the VS.

In general, we have to negate in immediate values we pass in because
the src1 negate field in the register description is in the bits3 slot
that the 32-bit value is loaded into, so it's ignored by the hardware.
However, the src0 negate field is in bits1, so after we'd negated the
immediate value loaded in, it would also get negated through the
register description.  This broke this VP instruction in the position
calculation in civ4:

MAD TEMP[1], TEMP[1], CONST[256].zzzz, CONST[256].-y-y-y-y;

Bug #30156

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index a64188afc561dc811209c630b834a7d30598cf95..fe9737d043a833f676f63186da221c4971f06839 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1426,11 +1426,10 @@ static struct brw_reg get_arg( struct brw_vs_compile *c,
                                          GET_SWZ(src->Swizzle, 1),
                                          GET_SWZ(src->Swizzle, 2),
                                          GET_SWZ(src->Swizzle, 3));
-   }
 
-   /* Note this is ok for non-swizzle instructions: 
-    */
-   reg.negate = src->Negate ? 1 : 0;   
+      /* Note this is ok for non-swizzle ARB_vp instructions */
+      reg.negate = src->Negate ? 1 : 0;
+   }
 
    return reg;
 }