Added support for "keep" attributes on wires

diff --git a/README b/README
index ef482b0f1b98fb7d6f33acc7d2e8865da1206d8d..3e49998a40567fa8d654cd5e7d7c1eeb9cdc85b2 100644 (file)
--- a/README
+++ b/README
@@ -254,9 +254,9 @@ Verilog Attributes and non-standard features
   passes to identify input and output ports of cells. The verilog backend
   also does not output placeholder modules on default.
 
-- The "keep" attribute on cells is used to mark cells that should never be
-  removed by the optimizer. This is used for example for cells that have
-  hidden connections that are not part of the netlist, such as IO pads.
+- The "keep" attribute on cells and wires is used to mark objects that should
+  never be removed by the optimizer. This is used for example for cells that
+  have hidden connections that are not part of the netlist, such as IO pads.
 
 - In addition to the (* ... *) attribute syntax, yosys supports
   the non-standard {* ... *} attribute syntax to set default attributes

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 3d75b64047daa446583ba8f81eb1e55dbe721aea..8e3691b34a1a5df22775f675a5cd720b2ce7a7bf 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -190,6 +190,11 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
                        if (!wire->port_input)
                                used_signals_nodrivers.add(sig);
                }
+               if (wire->get_bool_attribute("\\keep")) {
+                       RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
+                       assign_map.apply(sig);
+                       used_signals.add(sig);
+               }
        }
 
        std::vector<RTLIL::Wire*> del_wires;