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+From: bugzilla-daemon@libre-soc.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Mon, 25 May 2020 11:57:49 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords:
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution:
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: cestrauss@gmail.com
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+X-Bugzilla-Changed-Fields: assigned_to
+Message-ID: <bug-350-13-plsd4xOHus@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-350-13@https.bugs.libre-soc.org/>
+References: <bug-350-13@https.bugs.libre-soc.org/>
+X-Bugzilla-URL: https://bugs.libre-soc.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support
+ zeroing on RA
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