clean: ignore specify-s inside cells when determining whether to keep
authorEddie Hung <eddie@fpgeh.com>
Wed, 19 Feb 2020 18:45:10 +0000 (10:45 -0800)
committerEddie Hung <eddie@fpgeh.com>
Wed, 19 Feb 2020 18:45:10 +0000 (10:45 -0800)
passes/opt/opt_clean.cc
tests/various/specify.ys

index 2f69b3d4c1b2d70b24165e3c831b42f53bf19c63..f5bb40050ab4a29529b5a3d22ccc8d98ea0c1752 100644 (file)
@@ -51,20 +51,26 @@ struct keep_cache_t
                if (cache.count(module))
                        return cache.at(module);
 
-               cache[module] = true;
-               if (!module->get_bool_attribute(ID::keep)) {
-                       bool found_keep = false;
+               bool found_keep = false;
+               if (module->get_bool_attribute(ID::keep))
+                       found_keep = true;
+               else
                        for (auto cell : module->cells())
-                               if (query(cell)) found_keep = true;
-                       cache[module] = found_keep;
-               }
+                               if (query(cell, true /* ignore_specify */)) {
+                                       found_keep = true;
+                                       break;
+                               }
+               cache[module] = found_keep;
 
-               return cache[module];
+               return found_keep;
        }
 
-       bool query(Cell *cell)
+       bool query(Cell *cell, bool ignore_specify = false)
        {
-               if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($specify2), ID($specify3), ID($specrule)))
+               if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
+                       return true;
+
+               if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
                        return true;
 
                if (cell->has_keep_attr())
index a2b6038e47e81f95701e4a55c4aaa3ffb600acda..9d55b8eb5924a5af179d3418e2b41f01c3904b2b 100644 (file)
@@ -55,4 +55,23 @@ equiv_induct -seq 5
 equiv_status -assert
 design -reset
 
-read_verilog specify.v
+read_verilog -specify <<EOT
+(* blackbox *)
+module test7_sub(input i, output o);
+specify
+    (i => o) = 1;
+endspecify
+assign o = ~i;
+endmodule
+
+module test7(input i, output o);
+    wire w;
+    test7_sub unused(i, w);
+    test7_sub used(i, o);
+endmodule
+EOT
+hierarchy
+cd test7
+clean
+select -assert-count 1 c:used
+select -assert-none c:* c:used %d