LiteXXX cores: use format in prints

diff --git a/misoclib/com/liteeth/example_designs/test/test_regs.py b/misoclib/com/liteeth/example_designs/test/test_regs.py
index f2685cf54ad33fd91803ce3942a22b707789b116..6432242c553115f9b268db5c6fec46dab9b48590 100644 (file)
--- a/misoclib/com/liteeth/example_designs/test/test_regs.py
+++ b/misoclib/com/liteeth/example_designs/test/test_regs.py
@@ -2,9 +2,9 @@ def main(wb):
        wb.open()
        regs = wb.regs
        ###
-       print("sysid     : 0x%04x" %regs.identifier_sysid.read())
-       print("revision  : 0x%04x" %regs.identifier_revision.read())
-       print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
+       print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
+       print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
+       print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
        SRAM_BASE = 0x02000000
        wb.write(SRAM_BASE, [i for i in range(64)])
        print(wb.read(SRAM_BASE, 64))

diff --git a/misoclib/mem/litesata/example_designs/test/test_regs.py b/misoclib/mem/litesata/example_designs/test/test_regs.py
index c0ef387fea4cb528dd64ef2121e2e2e914db64bc..b416d677b76b8143c9c6a0f582904484703342ee 100644 (file)
--- a/misoclib/mem/litesata/example_designs/test/test_regs.py
+++ b/misoclib/mem/litesata/example_designs/test/test_regs.py
@@ -2,8 +2,8 @@ def main(wb):
        wb.open()
        regs = wb.regs
        ###
-       print("sysid     : 0x%04x" %regs.identifier_sysid.read())
-       print("revision  : 0x%04x" %regs.identifier_revision.read())
-       print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
+       print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
+       print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
+       print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
        ###
        wb.close()

diff --git a/misoclib/tools/litescope/example_designs/test/test_regs.py b/misoclib/tools/litescope/example_designs/test/test_regs.py
index c0ef387fea4cb528dd64ef2121e2e2e914db64bc..b416d677b76b8143c9c6a0f582904484703342ee 100644 (file)
--- a/misoclib/tools/litescope/example_designs/test/test_regs.py
+++ b/misoclib/tools/litescope/example_designs/test/test_regs.py
@@ -2,8 +2,8 @@ def main(wb):
        wb.open()
        regs = wb.regs
        ###
-       print("sysid     : 0x%04x" %regs.identifier_sysid.read())
-       print("revision  : 0x%04x" %regs.identifier_revision.read())
-       print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
+       print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
+       print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
+       print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
        ###
        wb.close()