+2013-09-16 Will Newton <will.newton@linaro.org>
+
+ * config/tc-arm.c (do_neon_ld_st_interleave): Add constraint
+ disallowing element size 64 with interleave other than 1.
+
2013-09-12 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* config/tc-mips.c (match_insn): Set error when $31 is used for
typebits = typetable[idx];
constraint (typebits == -1, _("bad list type for instruction"));
+ constraint (((inst.instruction >> 8) & 3) && et.size == 64,
+ _("bad element type for instruction"));
inst.instruction &= ~0xf00;
inst.instruction |= typebits << 8;
+2013-09-16 Will Newton <will.newton@linaro.org>
+
+ * gas/arm/neon-ldst-es.d: Add VLD1.64 instructions.
+ * gas/arm/neon-ldst-es.s: Likewise.
+ * testsuite/gas/arm/neon-ldst-es-bad.d: New file.
+ * testsuite/gas/arm/neon-ldst-es-bad.l: Likewise.
+ * testsuite/gas/arm/neon-ldst-es-bad.s: Likewise.
+
2013-09-12 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* gas/mips/bltzal.s: New file.
--- /dev/null
+# name: Bad element size combinations in Neon load/store instructions
+# as: -mfpu=neon
+# error-output: neon-ldst-es-bad.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:2: Error: bad type in Neon instruction -- `vld1\.64 {d0\[1\]},\[r0\]'
+[^:]*:3: Error: bad type in Neon instruction -- `vld1\.64 {d0\[\]},\[r0\]'
+[^:]*:4: Error: bad type in Neon instruction -- `vld2\.64 {d0\[1\]},\[r0\]'
+[^:]*:5: Error: bad type in Neon instruction -- `vld2\.64 {d0\[\]},\[r0\]'
+[^:]*:6: Error: bad element type for instruction -- `vld2\.64 {d0-d1},\[r0\]'
+[^:]*:7: Error: bad type in Neon instruction -- `vld3\.64 {d0\[1\]},\[r0\]'
+[^:]*:8: Error: bad type in Neon instruction -- `vld3\.64 {d0\[\]},\[r0\]'
+[^:]*:9: Error: bad element type for instruction -- `vld3\.64 {d0-d2},\[r0\]'
+[^:]*:10: Error: bad type in Neon instruction -- `vld4\.64 {d0\[1\]},\[r0\]'
+[^:]*:11: Error: bad type in Neon instruction -- `vld4\.64 {d0\[\]},\[r0\]'
+[^:]*:12: Error: bad element type for instruction -- `vld4\.64 {d0-d3},\[r0\]'
--- /dev/null
+ .text
+ vld1.64 {d0[1]}, [r0]
+ vld1.64 {d0[]}, [r0]
+ vld2.64 {d0[1]}, [r0]
+ vld2.64 {d0[]}, [r0]
+ vld2.64 {d0-d1}, [r0]
+ vld3.64 {d0[1]}, [r0]
+ vld3.64 {d0[]}, [r0]
+ vld3.64 {d0-d2}, [r0]
+ vld4.64 {d0[1]}, [r0]
+ vld4.64 {d0[]}, [r0]
+ vld4.64 {d0-d3}, [r0]
0[0-9a-f]+ <[^>]+> f427208f vld4\.32 {d2-d5}, \[r7\]
0[0-9a-f]+ <[^>]+> f467c08f vld4\.32 {d28-d31}, \[r7\]
0[0-9a-f]+ <[^>]+> f4a21c83 vld1\.32 {d1\[\]}, \[r2\], r3
+0[0-9a-f]+ <[^>]+> f42007cf vld1\.64 {d0}, \[r0\]
+0[0-9a-f]+ <[^>]+> f42002cf vld1\.64 {d0-d3}, \[r0\]
@ PR 14987 and 14887: Allow for whitespace in the instruction.
vld1.32 { d1 [ ] } , [ r2 ] , r3
+
+ vld1.64 {d0}, [r0]
+ vld1.64 {d0-d3}, [r0]