the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
- calling convention in 64 bit mode. It doesn't work though, and should
- be replaced with something better designed. */
-
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "target-def.h"
#include "integrate.h"
-#ifdef __GNU_STAB__
-#define STAB_CODE_TYPE enum __stab_debug_code
-#else
-#define STAB_CODE_TYPE int
-#endif
-
-extern tree lookup_name PARAMS ((tree));
-
/* Enumeration for all of the relational tests, so that we can build
arrays indexed by the test type, and not worry about the order
of EQ, NE, etc. */
rtx *, rtx));
static void mips_avoid_hazards PARAMS ((void));
static void mips_reorg PARAMS ((void));
-static void abort_with_insn PARAMS ((rtx, const char *))
- ATTRIBUTE_NORETURN;
static int symbolic_expression_p PARAMS ((rtx));
static bool mips_assemble_integer PARAMS ((rtx, unsigned int, int));
static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
const char *mips_isa_string; /* for -mips{1,2,3,4} */
const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
-/* Whether we are generating mips16 code. This is a synonym for
- TARGET_MIPS16, and exists for use as an attribute. */
-int mips16;
-
/* This variable is set by -mno-mips16. We only care whether
-mno-mips16 appears or not, and using a string in this fashion is
just a way to avoid using up another bit in target_flags. */
/* If TRUE, we split addresses into their high and low parts in the RTL. */
int mips_split_addresses;
-/* Generating calls to position independent functions? */
-enum mips_abicalls_type mips_abicalls;
-
/* Mode used for saving/restoring general purpose registers. */
static enum machine_mode gpr_mode;
};
/* Map register constraint character to register class. */
-enum reg_class mips_char_to_class[256] =
-{
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
-};
+enum reg_class mips_char_to_class[256];
\f
/* A table describing all the processors gcc knows about. Names are
matched in the order listed. The first mention of an ISA level is
return const_arith_operand (op, mode) || register_operand (op, mode);
}
-/* Return truth value of whether OP can be used as an operand in a two
- address arithmetic insn (such as set 123456,%o4) of mode MODE. */
-
-int
-arith32_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- if (GET_CODE (op) == CONST_INT)
- return 1;
-
- return register_operand (op, mode);
-}
-
/* Return truth value of whether OP is an integer which fits in 16 bits. */
int
return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
}
-/* Return truth value of whether OP is a 32 bit integer which is too big to
- be loaded with one instruction. */
-
-int
-large_int (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- HOST_WIDE_INT value;
-
- if (GET_CODE (op) != CONST_INT)
- return 0;
-
- value = INTVAL (op);
-
- /* ior reg,$r0,value */
- if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
- return 0;
-
- /* subu reg,$r0,value */
- if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
- return 0;
-
- /* lui reg,value>>16 */
- if ((value & 0x0000ffff) == 0)
- return 0;
-
- return 1;
-}
-
/* Return truth value of whether OP is a register or the constant 0.
In mips16 mode, we only accept a register, since the mips16 does
not have $0. */
}
}
-/* Return truth value of whether OP is a register or the constant 0,
- even in mips16 mode. */
-
-int
-true_reg_or_0_operand (op, mode)
- rtx op;
- enum machine_mode mode;
-{
- switch (GET_CODE (op))
- {
- case CONST_INT:
- return INTVAL (op) == 0;
-
- case CONST_DOUBLE:
- return op == CONST0_RTX (mode);
-
- default:
- return register_operand (op, mode);
- }
-}
-
/* Accept the floating point constant 1 in the appropriate mode. */
int
return CONSTANT_P (op);
}
-/* Coprocessor operand; return true if rtx is a REG and refers to a
- coprocessor. */
-
-int
-coprocessor_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return (GET_CODE (op) == REG
- && COP0_REG_FIRST <= REGNO (op)
- && REGNO (op) <= COP3_REG_LAST);
-}
-
-int
-coprocessor2_operand (op, mode)
- rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
-{
- return (GET_CODE (op) == REG
- && COP2_REG_FIRST <= REGNO (op)
- && REGNO (op) <= COP2_REG_LAST);
-}
-
/* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
possibly with an offset. */
break;
default:
- abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
+ fatal_insn ("bad test", gen_rtx (test_code, VOIDmode, cmp0, cmp1));
}
/* Generate the branch. */
}
}
\f
-/* Abort after printing out a specific insn. */
-
-static void
-abort_with_insn (insn, reason)
- rtx insn;
- const char *reason;
-{
- error (reason);
- debug_rtx (insn);
- abort ();
-}
-\f
/* Set up globals to generate code for the ISA or processor
described by INFO. */
implemented. */
if (TARGET_ABICALLS)
{
- mips_abicalls = MIPS_ABICALLS_YES;
if (flag_pic == 0)
flag_pic = 1;
if (mips_section_threshold > 0)
warning ("-G is incompatible with PIC code which is the default");
}
- else
- mips_abicalls = MIPS_ABICALLS_NO;
/* The MIPS and SGI o32 assemblers expect small-data variables to
be declared before they are used. Although we once had code to
mips_entry = 1;
}
- /* We copy TARGET_MIPS16 into the mips16 global variable, so that
- attributes can access it. */
- if (TARGET_MIPS16)
- mips16 = 1;
- else
- mips16 = 0;
-
/* When using explicit relocs, we call dbr_schedule from within
mips_reorg. */
if (TARGET_EXPLICIT_RELOCS)
/* sdbout_parms does not want this to crash for unrecognized cases. */
#if 0
else if (reg != arg_pointer_rtx)
- abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer");
+ fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
+ addr);
#endif
return offset;
code = GET_CODE (op);
- if (code == SIGN_EXTEND)
- op = XEXP (op, 0), code = GET_CODE (op);
-
if (letter == 'R')
{
if (TARGET_ABICALLS && TARGET_NEWABI)
case LTU: fputs ("ltu", file); break;
case LEU: fputs ("leu", file); break;
default:
- abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
+ fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
}
else if (letter == 'N')
case LTU: fputs ("geu", file); break;
case LEU: fputs ("gtu", file); break;
default:
- abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
+ fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
}
else if (letter == 'F')
case EQ: fputs ("c1f", file); break;
case NE: fputs ("c1t", file); break;
default:
- abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
+ fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
}
else if (letter == 'W')
case EQ: fputs ("c1t", file); break;
case NE: fputs ("c1f", file); break;
default:
- abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
+ fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
}
else if (letter == 'S')
pattern = RTVEC_ELT (adjust, i);
if (GET_CODE (pattern) != SET
|| GET_CODE (SET_SRC (pattern)) != ASHIFT)
- abort_with_insn (pattern, "insn is not a shift");
+ fatal_insn ("insn is not a shift", pattern);
PUT_CODE (SET_SRC (pattern), ASHIFTRT);
insn = emit_insn (pattern);
int regno = -1;
int gp_reg_p;
- if (GET_CODE (x) == SIGN_EXTEND)
- {
- int off = 0;
-
- x = XEXP (x, 0);
-
- /* We may be called with reg_renumber NULL from regclass.
- ??? This is probably a bug. */
- if (reg_renumber)
- regno = true_regnum (x);
- else
- {
- while (GET_CODE (x) == SUBREG)
- {
- off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
- GET_MODE (SUBREG_REG (x)),
- SUBREG_BYTE (x),
- GET_MODE (x));
- x = SUBREG_REG (x);
- }
-
- if (GET_CODE (x) == REG)
- regno = REGNO (x) + off;
- }
-
- /* 64-bit floating-point registers don't store 32-bit values
- in sign-extended form. The only way we can reload
- (sign_extend:DI (reg:SI $f0)) is by moving $f0 into
- an integer register using a 32-bit move. */
- if (FP_REG_P (regno))
- return (class == GR_REGS ? NO_REGS : GR_REGS);
-
- /* For the same reason, we can only reload (sign_extend:DI FOO) into
- a floating-point register when FOO is an integer register. */
- if (class == FP_REGS)
- return (GP_REG_P (regno) ? NO_REGS : GR_REGS);
- }
-
- else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
regno = true_regnum (x);
gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
return "";
}
- /* We do not currently use this code. It handles jumps to
- arbitrary locations, using `jr', even across a 256MB boundary.
- We could add a -mhuge switch, and then use this code instead of
- the `j' alternative above when -mhuge was used. */
-#if 0
- case 16:
- case 20:
- {
- /* Generate a reversed conditional branch around a `jr'
- instruction:
-
- .set noreorder
- .set nomacro
- .set noat
- bc l
- la $at, target
- jr $at
- .set at
- .set macro
- .set reorder
- l:
-
- Not pretty, but allows a conditional branch anywhere in the
- 32-bit address space. If the original branch is annulled,
- then the instruction in the delay slot should be executed
- only if the branch is taken. The la instruction is really
- a macro which will usually take eight bytes, but sometimes
- takes only four, if the instruction to which we're jumping
- gets its own entry in the global pointer table, which will
- happen if its a case label. The assembler will then
- generate only a four-byte sequence, rather than eight, and
- there seems to be no way to tell it not to. Thus, we can't
- just use a `.+x' addressing form; we don't know what value
- to give for `x'.
-
- So, we resort to using the explicit relocation syntax
- available in the assembler and do:
-
- lw $at,%got_page(target)($gp)
- daddiu $at,$at,%got_ofst(target)
-
- That way, this always takes up eight bytes, and we can use
- the `.+x' form. Of course, these explicit machinations
- with relocation will not work with old assemblers. Then
- again, neither do out-of-range branches, so we haven't lost
- anything. */
-
- /* The target of the reversed branch. */
- const char *const target
- = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
- const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
- const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
- char *c;
-
- strcpy (buffer, "%(%<%[");
- c = strchr (buffer, '\0');
- /* Generate the reversed comparison. This takes four
- bytes. */
- if (float_p)
- sprintf (c, "%%*b%s\t%%Z2%s",
- inverted_p ? comp : inverted_comp,
- target);
- else
- sprintf (c, "%%*b%s%s\t%s%s,%s",
- inverted_p ? comp : inverted_comp,
- need_z_p ? "z" : "",
- op1,
- op2,
- target);
- c = strchr (buffer, '\0');
- /* Generate the load-address, and jump. This takes twelve
- bytes, for a total of 16. */
- sprintf (c,
- "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
- at_register,
- gp_register,
- at_register,
- at_register,
- at_register);
- if (length == 20)
- /* The delay slot was unfilled. Since we're inside
- .noreorder, the assembler will not fill in the NOP for
- us, so we must do it ourselves. */
- strcat (buffer, "\n\tnop");
- strcat (buffer, "%]%>%)");
- return buffer;
- }
-#endif
-
default:
abort ();
}
/* Standard GCC variables that we reference. */
-extern char call_used_regs[];
-extern int may_call_alloca;
extern int target_flags;
/* MIPS external variables defined in mips.c. */
PROCESSOR_SR71000
};
-/* Recast the cpu class to be the cpu attribute. */
-#define mips_cpu_attr ((enum attr_cpu)mips_tune)
-
/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
to work on a 64 bit machine. */
#define ABI_EABI 3
#define ABI_O64 4
-/* Whether to emit abicalls code sequences or not. */
-
-enum mips_abicalls_type {
- MIPS_ABICALLS_NO,
- MIPS_ABICALLS_YES
-};
-
-/* Recast the abicalls class to be the abicalls attribute. */
-#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
-
/* Information about one recognized processor. Defined here for the
benefit of TARGET_CPU_CPP_BUILTINS. */
struct mips_cpu_info {
extern enum cmp_type branch_type; /* what type of branch to use */
extern enum processor_type mips_arch; /* which cpu to codegen for */
extern enum processor_type mips_tune; /* which cpu to schedule for */
-extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
extern int mips_isa; /* architectural level */
-extern int mips16; /* whether generating mips16 code */
extern int mips16_hard_float; /* mips16 without -msoft-float */
extern int mips_entry; /* generate entry/exit for mips16 */
extern const char *mips_arch_string; /* for -march=<xxx> */
which write to the HI and LO registers. Most targets require a
two-instruction gap. */
#define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
-
-/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
- -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
- -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
- target_flags, and -mgp64 sets MASK_64BIT.
-
- Setting MASK_64BIT in target_flags will cause gcc to assume that
- registers are 64 bits wide. int, long and void * will be 32 bit;
- this may be changed with -mint64 or -mlong64.
-
- The gen* programs link code that refers to MASK_64BIT. They don't
- actually use the information in target_flags; they just refer to
- it. */
\f
/* Switch Recognition by gcc.c. Add -G xx support */
%(target_asm_spec) \
%(subtarget_asm_spec)"
-/* Specify to run a post-processor, mips-tfile after the assembler
- has run to stuff the mips debug information into the object file.
- This is needed because the $#!%^ MIPS assembler provides no way
- of specifying such information in the assembly file. If we are
- cross compiling, disable mips-tfile unless the user specifies
- -mmips-tfile. */
-
-#ifndef ASM_FINAL_SPEC
-#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
-/* GAS */
-#define ASM_FINAL_SPEC "\
-%{mmips-as: %{!mno-mips-tfile: \
- \n mips-tfile %{v*: -v} \
- %{K: -I %b.o~} \
- %{!K: %{save-temps: -I %b.o~}} \
- %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
- %{.s:%i} %{!.s:%g.s}}}"
-
-#else
-/* not GAS */
-#define ASM_FINAL_SPEC "\
-%{!mgas: %{!mno-mips-tfile: \
- \n mips-tfile %{v*: -v} \
- %{K: -I %b.o~} \
- %{!K: %{save-temps: -I %b.o~}} \
- %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
- %{.s:%i} %{!.s:%g.s}}}"
-
-#endif
-#endif /* ASM_FINAL_SPEC */
-
-/* Redefinition of libraries used. Mips doesn't support normal
- UNIX style profiling via calling _mcount. It does offer
- profiling that samples the PC, so do what we can... */
-
-#ifndef LIB_SPEC
-#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
-#endif
-
/* Extra switches sometimes passed to the linker. */
/* ??? The bestGnum will never be passed to the linker, because the gcc driver
will interpret it as a -b option. */
#endif
/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
-/* Note, we will need to adjust the following if we ever find a MIPS variant
- that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
- that show up in this case. */
#ifndef CC1_SPEC
#define CC1_SPEC "\
#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
#endif
-\f
-/* Print subsidiary information on the compiler version in use. */
-
-#define MIPS_VERSION "[AL 1.1, MM 40]"
-
-#ifndef MACHINE_TYPE
-#define MACHINE_TYPE "BSD Mips"
-#endif
-
-#ifndef TARGET_VERSION_INTERNAL
-#define TARGET_VERSION_INTERNAL(STREAM) \
- fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
-#endif
-
-#ifndef TARGET_VERSION
-#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
-#endif
-
\f
#define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
#define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
== (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
-/* MIPS pc is not overloaded on a register. */
-/* #define PC_REGNUM xx */
-
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
-/* Offset from the stack pointer to the first available location. Use
- the default value zero. */
-/* #define STACK_POINTER_OFFSET 0 */
-
/* Base register for access to local variables of the function. We
pretend that the frame pointer is $1, and then eliminate it to
HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
a fixed register, and will not be used for anything else. */
#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
-/* Temporary scratch register for use by the assembler. */
-#define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
-
/* $30 is not available on the mips16, so we use $17 as the frame
pointer. */
#define HARD_FRAME_POINTER_REGNUM \
/* Register in which static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
-/* If the structure value address is passed in a register, then
- `STRUCT_VALUE_REGNUM' should be the number of that register. */
-/* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
-
/* If the structure value address is not passed in a register, define
`STRUCT_VALUE' as an expression returning an RTX for the place
where the address is passed. If it returns 0, the address is
+ (TARGET_ABICALLS && !TARGET_NEWABI \
? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
-/* Offset from the stack pointer register to an item dynamically
- allocated on the stack, e.g., by `alloca'.
-
- The default value for this macro is `STACK_POINTER_OFFSET' plus the
- length of the outgoing arguments. The default is correct for most
- machines. See `function.c' for details.
-
- The MIPS ABI states that functions which dynamically allocate the
- stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
- we are trying to create a second frame pointer to the function, so
- allocate some stack space to make it happy.
-
- However, the linker currently complains about linking any code that
- dynamically allocates stack space, and there seems to be a bug in
- STACK_DYNAMIC_OFFSET, so don't define this right now. */
-
-#if 0
-#define STACK_DYNAMIC_OFFSET(FUNDECL) \
- ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
- ? 4*UNITS_PER_WORD \
- : current_function_outgoing_args_size)
-#endif
-
/* The return address for the current frame is in r31 if this is a leaf
function. Otherwise, it is on the stack. It is at a variable offset
from sp/fp/ap, so we define a fake hard register rap which is a
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
(OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by.
- On the VAX, sp@- in a byte insn really pushes a word. */
-
-/* #define PUSH_ROUNDING(BYTES) 0 */
-
/* If defined, the maximum amount of space required for outgoing
arguments will be computed and placed into the variable
`current_function_outgoing_args_size'. No space will be pushed
{"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
{"const_arith_operand", { CONST, CONST_INT }}, \
{"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
- {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
{"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
- {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
{"small_int", { CONST_INT }}, \
- {"large_int", { CONST_INT }}, \
{"mips_const_double_ok", { CONST_DOUBLE }}, \
{"const_float_1_operand", { CONST_DOUBLE }}, \
{"simple_memory_operand", { MEM, SUBREG }}, \
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