Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position

write_verilog: fix placement of case attributes

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6288502a549bd6efd445e5a5cb310f95bbda950b..087c6fec6cf4069bcd5236fe17e1ac5af39474d7 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1501,6 +1501,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 
        bool got_default = false;
        for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
+               dump_attributes(f, indent + "  ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true);
                if ((*it)->compare.size() == 0) {
                        if (got_default)
                                continue;
@@ -1514,9 +1515,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
                                dump_sigspec(f, (*it)->compare[i]);
                        }
                }
-               f << stringf(":");
-               dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true);
-               f << stringf("\n");
+               f << stringf(":\n");
                dump_case_body(f, indent + "    ", *it);
        }