register output corrected

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 2c8546f05e0dafeb78c8b21eb8379b84563106ee..03ef183a5ac4332aa39ff049aad31ac9ce0f7214 100644 (file)
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -647,7 +647,7 @@ struct BtorDumper
                                log(" - width is %d\n", output_width);
                                int cond = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1);
                                bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-                               const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\D"));
+                               const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q"));
                                int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width);
                                unsigned start_bit = 0;
                                for(unsigned i=0; i<cell_output->chunks.size(); ++i)