i386: Skip ENDBR32 at the target function entry

Skip ENDBR32 at the target function entry when initializing trampoline.

Tested on Linux/x86-64 CET machine with and without -m32.

gcc/

	PR target/93656
	* config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
	the target function entry.

gcc/testsuite/

	PR target/93656
	* gcc.target/i386/pr93656.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 41498390c21e0e130247c59898c5155938ebd323..d9fb2c81e0ed20294989498339f78bb32b369534 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-02-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/93656
+       * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
+       the target function entry.
+
 2020-02-13  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * common/config/arc/arc-common.c (arc_option_optimization_table):

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 44bc0e0176aa7a5d6b656381f311f35735665a40..dac7a3fc5fde9e0a7ae0c88b8ffe567d5c593013 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -16839,9 +16839,14 @@ ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
         the stack, we need to skip the first insn which pushes the
         (call-saved) register static chain; this push is 1 byte.  */
       offset += 5;
+      int skip = MEM_P (chain) ? 1 : 0;
+      /* Skip ENDBR32 at the entry of the target function.  */
+      if (need_endbr
+         && !cgraph_node::get (fndecl)->only_called_directly_p ())
+       skip += 4;
       disp = expand_binop (SImode, sub_optab, fnaddr,
                           plus_constant (Pmode, XEXP (m_tramp, 0),
-                                         offset - (MEM_P (chain) ? 1 : 0)),
+                                         offset - skip),
                           NULL_RTX, 1, OPTAB_DIRECT);
       emit_move_insn (mem, disp);
     }

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5ac858efb1b7748a1629a320fa933c17a57b2b81..c296fc3810947bbedfadf18851addea9edc7da97 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/93656
+       * gcc.target/i386/pr93656.c: New test.
+
 2020-02-13  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * gcc.target/arc/nps400-1.c: Update test.

diff --git a/gcc/testsuite/gcc.target/i386/pr93656.c b/gcc/testsuite/gcc.target/i386/pr93656.c
new file mode 100644 (file)
index 0000000..f0ac8c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr93656.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { ia32 && cet } } } */
+/* { dg-options "-O2 -fcf-protection" } */
+
+#include "pr67770.c"