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diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index d88c2b1323b8b123b204ec78e60e7eb6f6434c30..638eecd92d1eeb42e68b0bd617e47ae406ee303f 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -19,4 +19,14 @@ Dynamic SIMD ALUs for maximum performance and effectiveness.
 # Add and Subtract
 
 Surprisingly, no new additional instructions are required to perform
-a straightforward big-integer add or subtract.  Vectorised `addex`
+a straightforward big-integer add or subtract.  Vectorised `addeo`
+or `addex` is perfectly sufficient to produce arbitrary-length
+big-integer add due to the rules set in SVP64 that all Vector Operations
+are directly equivalent to the strict Program Order Execution of
+their element-level operations.
+
+Thus, due to sequential execution of `addeo` both consuming and producing
+a CA Flag, `sv.addeo` is in effect an alias for Vectorised add.  As such,
+implementors are entirely at liberty to recognise Horizontal-First Vector
+adds and send the vector of registers to a much larger and wider back-end
+ALU.