case Idle:
assert(old_status == Running);
- idleFraction++;
+ notIdleFraction--;
if (tickEvent.scheduled())
tickEvent.squash();
break;
assert(old_status == Idle ||
old_status == DcacheMissStall ||
old_status == IcacheMissComplete);
- if (old_status == Idle && curTick != 0)
- idleFraction--;
+ if (old_status == Idle)
+ notIdleFraction++;
if (tickEvent.squashed())
tickEvent.reschedule(curTick + 1);
.prereq(dcacheStallCycles)
;
+ idleFraction = constant(1.0) - notIdleFraction;
numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
simInsts += numInsts;
}
SimpleCPU::resetStats()
{
startNumInst = numInst;
+ notIdleFraction = (_status != Idle);
}
void
Counter startNumLoad;
// number of idle cycles
- Statistics::Average<> idleFraction;
+ Statistics::Average<> notIdleFraction;
+ Statistics::Formula idleFraction;
// number of cycles stalled for I-cache misses
Statistics::Scalar<> icacheStallCycles;