litex/build/sim: add tapcfg submodule for ethernet

diff --git a/.gitmodules b/.gitmodules
index 11034c7d215343be4d659346b3a83e11a10ca652..69988365be41d1345c7a1543c44eab3c4acaf17e 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,3 +10,6 @@
 [submodule "litex/soc/cores/cpu/picorv32/verilog"]
        path = litex/soc/cores/cpu/picorv32/verilog
        url = https://github.com/cliffordwolf/picorv32
+[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
+       path = litex/build/sim/core/modules/ethernet/tapcfg
+       url = https://github.com/nizox/tapcfg

diff --git a/litex/build/sim/core/modules/ethernet/tapcfg b/litex/build/sim/core/modules/ethernet/tapcfg
new file mode 160000 (submodule)
index 0000000..4ce399d
--- /dev/null
+++ b/litex/build/sim/core/modules/ethernet/tapcfg
@@ -0,0 +1 @@
+Subproject commit 4ce399deedc42a44f2854b29f8d34ebbd5d45872