stats: Update to match ARM ISA changes

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 1e2906ba45bc9fccd677d4203896a1dd724fe0b4..cf4e1ea1a697808e6d93b311c0d7d8e76d681815 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -47,6 +47,8 @@ phys_addr_range_64=40
 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -199,8 +201,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.checker]
 type=O3Checker
@@ -1181,6 +1190,7 @@ pio=system.iobus.master[5]
 type=SubSystem
 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.dcc.osc_cpu]
 type=RealViewOsc
@@ -1373,6 +1383,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview
@@ -1568,8 +1579,9 @@ pio=system.membus.master[4]
 
 [system.realview.mcc]
 type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.mcc.osc_clcd]
 type=RealViewOsc
@@ -1615,6 +1627,16 @@ position=0
 site=0
 voltage_domain=system.voltage_domain
 
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
index c53cbe481f0750f00542441840acd859cc8fe584..6cbcdcc79633c27b700f06dfb9fc940bdc0da61b 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
@@ -16,7 +16,7 @@ warn:         instruction 'mcr bpiallis' unimplemented
 warn:  instruction 'mcr icialluis' unimplemented
 warn:  instruction 'mcr dccimvac' unimplemented
 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: 11083490000: Instruction results do not match! (Values may not actually be integers) Inst: 0xa, checker: 0
+warn: 11084065000: Instruction results do not match! (Values may not actually be integers) Inst: 0xa, checker: 0
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
@@ -42,6 +42,6 @@ warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmcr
 warn: Ignoring write to miscreg pmcr
-warn: 409465425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
+warn: 409343110000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
 warn:  instruction 'mcr dcisw' unimplemented
 warn:  instruction 'mcr bpiall' unimplemented

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
index fde4d40f2c0ffe617e80d04d7220844d0eefeff7..87c07a72a7111706d4507130d6d3940e2a43552e 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
@@ -44,4 +44,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2832922792000 because m5_exit instruction encountered
+Exiting @ tick 2832862976500 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 11b022e8f96845c24baaac5a3d5a3ebdc66d29ab..1631918b9b3c10ebfa6d4c146d0d4014164bcb23 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.832863                       # Nu
 sim_ticks                                2832862976500                       # Number of ticks simulated
 final_tick                               2832862976500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  63021                       # Simulator instruction rate (inst/s)
-host_op_rate                                    76439                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1578508192                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 579360                       # Number of bytes of host memory used
-host_seconds                                  1794.65                       # Real time elapsed on the host
+host_inst_rate                                 104475                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126719                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2616817312                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 625044                       # Number of bytes of host memory used
+host_seconds                                  1082.56                       # Real time elapsed on the host
 sim_insts                                   113100501                       # Number of instructions simulated
 sim_ops                                     137180951                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -740,7 +740,7 @@ system.cpu.rename.IQFullEvents                  65507                       # Nu
 system.cpu.rename.LQFullEvents                  18530                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents               30752508                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands           150221263                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             676972712                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups             676943612                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        163957736                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups             10899                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             141737618                       # Number of HB maps that are committed
@@ -757,7 +757,7 @@ system.cpu.iq.iqNonSpecInstsAdded             2117732                       # Nu
 system.cpu.iq.iqInstsIssued                 143038678                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued            260968                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined         8155598                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14296072                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined     14294324                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved         121861                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     270560621                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         0.528675                       # Number of insts issued each cycle
@@ -979,7 +979,7 @@ system.cpu.fp_regfile_reads                      9529                       # nu
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                 502156067                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                 53129749                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               347863701                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               347855567                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                1521708                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements            838747                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.925928                       # Cycle average of tags in use

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index c9a130278ef9bcc6692fd67bdb1f5eb2101e9d7f..6af9f752e11e20730806485211bd4754f3110d71 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -47,6 +47,8 @@ phys_addr_range_64=40
 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -199,8 +201,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu0.dcache]
 type=Cache
@@ -846,8 +855,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu1.dcache]
 type=Cache
@@ -1499,14 +1515,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1533,6 +1549,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -1737,6 +1760,7 @@ pio=system.iobus.master[5]
 type=SubSystem
 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.dcc.osc_cpu]
 type=RealViewOsc
@@ -1929,6 +1953,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview
@@ -2124,8 +2149,9 @@ pio=system.membus.master[4]
 
 [system.realview.mcc]
 type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.mcc.osc_clcd]
 type=RealViewOsc
@@ -2171,6 +2197,16 @@ position=0
 site=0
 voltage_domain=system.voltage_domain
 
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index b6712dc146154c7ae92dc047a46603ccc2a79fe6..3e7bd42cea899588feb5729b75394de7f077438c 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
@@ -33,6 +33,7 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
 warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 warn: allocating bonus target for snoop
+warn: allocating bonus target for snoop
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index e3fd3e7c98987c53cd971913338e3757e8d288fd..5b77a63d302de599e78031929519e9e23cecd8ac 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2837474672000 because m5_exit instruction encountered
+Exiting @ tick 2825959731500 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 1ded9ce83240fac0b8e09150336064ef4e76f838..0e8d3a89864b8bcaf3c763a9b554cb1e5610602f 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.825960                       # Nu
 sim_ticks                                2825959731500                       # Number of ticks simulated
 final_tick                               2825959731500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71367                       # Simulator instruction rate (inst/s)
-host_op_rate                                    86573                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1679006506                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 618544                       # Number of bytes of host memory used
-host_seconds                                  1683.11                       # Real time elapsed on the host
+host_inst_rate                                 152939                       # Simulator instruction rate (inst/s)
+host_op_rate                                   185526                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3598106166                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 665816                       # Number of bytes of host memory used
+host_seconds                                   785.40                       # Real time elapsed on the host
 sim_insts                                   120118276                       # Number of instructions simulated
 sim_ops                                     145712235                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -639,7 +639,7 @@ system.cpu0.rename.IQFullEvents                164556                       # Nu
 system.cpu0.rename.LQFullEvents                 58179                       # Number of times rename has blocked due to LQ full
 system.cpu0.rename.SQFullEvents               6849429                       # Number of times rename has blocked due to SQ full
 system.cpu0.rename.RenamedOperands          141656181                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            634615161                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RenameLookups            634589847                       # Number of register rename lookups that rename has made
 system.cpu0.rename.int_rename_lookups       152645231                       # Number of integer rename lookups
 system.cpu0.rename.fp_rename_lookups             9369                       # Number of floating rename lookups
 system.cpu0.rename.CommittedMaps            130468277                       # Number of HB maps that are committed
@@ -656,7 +656,7 @@ system.cpu0.iq.iqNonSpecInstsAdded            1713414                       # Nu
 system.cpu0.iq.iqInstsIssued                132756465                       # Number of instructions issued
 system.cpu0.iq.iqSquashedInstsIssued           452944                       # Number of squashed instructions issued
 system.cpu0.iq.iqSquashedInstsExamined       10581179                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     21721412                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedOperandsExamined     21719888                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.iq.iqSquashedNonSpecRemoved        120083                       # Number of squashed non-spec instructions that were removed
 system.cpu0.iq.issued_per_cycle::samples    198828221                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::mean        0.667694                       # Number of insts issued each cycle
@@ -777,9 +777,9 @@ system.cpu0.iew.iewDispNonSpecInsts            875924                       # Nu
 system.cpu0.iew.iewIQFullEvents                 28511                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents               132116                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents         19339                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        261904                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        261906                       # Number of branches that were predicted taken incorrectly
 system.cpu0.iew.predictedNotTakenIncorrect       398193                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              660097                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.branchMispredicts              660099                       # Number of branch mispredicts detected at execute
 system.cpu0.iew.iewExecutedInsts            131724041                       # Number of executed instructions
 system.cpu0.iew.iewExecLoadInsts             23895876                       # Number of load instructions executed
 system.cpu0.iew.iewExecSquashedInsts           965291                       # Number of squashed instructions skipped in execute
@@ -878,7 +878,7 @@ system.cpu0.fp_regfile_reads                     8185                       # nu
 system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
 system.cpu0.cc_regfile_reads                464897652                       # number of cc regfile reads
 system.cpu0.cc_regfile_writes                49725456                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              274171027                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads              274163615                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes               1224889                       # number of misc regfile writes
 system.cpu0.dcache.tags.replacements           709828                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          497.174198                       # Cycle average of tags in use
@@ -1860,7 +1860,7 @@ system.cpu1.rename.IQFullEvents                 36982                       # Nu
 system.cpu1.rename.LQFullEvents                 15461                       # Number of times rename has blocked due to LQ full
 system.cpu1.rename.SQFullEvents               1675349                       # Number of times rename has blocked due to SQ full
 system.cpu1.rename.RenamedOperands           22265644                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            103654423                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RenameLookups            103648875                       # Number of register rename lookups that rename has made
 system.cpu1.rename.int_rename_lookups        25648399                       # Number of integer rename lookups
 system.cpu1.rename.fp_rename_lookups             1667                       # Number of floating rename lookups
 system.cpu1.rename.CommittedMaps             19867778                       # Number of HB maps that are committed
@@ -1877,7 +1877,7 @@ system.cpu1.iq.iqNonSpecInstsAdded             559995                       # Nu
 system.cpu1.iq.iqInstsIssued                 21251983                       # Number of instructions issued
 system.cpu1.iq.iqSquashedInstsIssued            91992                       # Number of squashed instructions issued
 system.cpu1.iq.iqSquashedInstsExamined        2044542                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      4727165                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedOperandsExamined      4726903                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu1.iq.iqSquashedNonSpecRemoved         43295                       # Number of squashed non-spec instructions that were removed
 system.cpu1.iq.issued_per_cycle::samples     34136181                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::mean        0.622565                       # Number of insts issued each cycle
@@ -2099,7 +2099,7 @@ system.cpu1.fp_regfile_reads                     1401                       # nu
 system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
 system.cpu1.cc_regfile_reads                 75464831                       # number of cc regfile reads
 system.cpu1.cc_regfile_writes                 6816973                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads               50047969                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads               50047460                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                387254                       # number of misc regfile writes
 system.cpu1.dcache.tags.replacements           189214                       # number of replacements
 system.cpu1.dcache.tags.tagsinuse          472.223119                       # Cycle average of tags in use

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index dead082fc45bdccab0d05dbaa409ec3daacc5e26..cf234591c3e71e73893f1d9d03720440c3134dc6 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -47,6 +47,8 @@ phys_addr_range_64=40
 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -199,8 +201,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.dcache]
 type=Cache
@@ -1029,6 +1038,7 @@ pio=system.iobus.master[5]
 type=SubSystem
 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.dcc.osc_cpu]
 type=RealViewOsc
@@ -1221,6 +1231,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview
@@ -1416,8 +1427,9 @@ pio=system.membus.master[4]
 
 [system.realview.mcc]
 type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.mcc.osc_clcd]
 type=RealViewOsc
@@ -1463,6 +1475,16 @@ position=0
 site=0
 voltage_domain=system.voltage_domain
 
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index c85683f6b4143d674812d1423b79da9f2a22707f..76b741f0aa1b2f282080ef49e2642f862e19a2b5 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2832922792000 because m5_exit instruction encountered
+Exiting @ tick 2832862976500 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index a08043e3c2e361afd5302e5c1987c026c5c39d7c..690dc124ee700f779d7cc672879b76e89eace68c 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.832863                       # Nu
 sim_ticks                                2832862976500                       # Number of ticks simulated
 final_tick                               2832862976500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  70501                       # Simulator instruction rate (inst/s)
-host_op_rate                                    85511                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1765850548                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 578080                       # Number of bytes of host memory used
-host_seconds                                  1604.25                       # Real time elapsed on the host
+host_inst_rate                                 159961                       # Simulator instruction rate (inst/s)
+host_op_rate                                   194019                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4006592882                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 625056                       # Number of bytes of host memory used
+host_seconds                                   707.05                       # Real time elapsed on the host
 sim_insts                                   113100501                       # Number of instructions simulated
 sim_ops                                     137180951                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -601,7 +601,7 @@ system.cpu.rename.IQFullEvents                  65507                       # Nu
 system.cpu.rename.LQFullEvents                  18530                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents               30752508                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands           150221263                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             676972712                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups             676943612                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        163957736                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups             10899                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             141737618                       # Number of HB maps that are committed
@@ -618,7 +618,7 @@ system.cpu.iq.iqNonSpecInstsAdded             2117732                       # Nu
 system.cpu.iq.iqInstsIssued                 143038678                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued            260968                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined         8155598                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14296072                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined     14294324                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved         121861                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     270560621                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         0.528675                       # Number of insts issued each cycle
@@ -840,7 +840,7 @@ system.cpu.fp_regfile_reads                      9529                       # nu
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                 502156061                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                 53129749                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               347863701                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               347855567                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                1521708                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements            838747                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.925928                       # Cycle average of tags in use

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
index 4d37af833f53f16d10e33d33984e16c432dcbe5b..9d9d131ca35acb29ba9fc0a3dafda461c6bbfa65 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -47,6 +47,8 @@ phys_addr_range_64=40
 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -552,11 +554,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu2.dstage2_mmu]
 type=ArmStage2MMU
@@ -1155,11 +1164,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu3.dstage2_mmu]
 type=ArmStage2MMU
@@ -1690,14 +1706,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1724,6 +1740,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -1928,6 +1951,7 @@ pio=system.iobus.master[5]
 type=SubSystem
 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.dcc.osc_cpu]
 type=RealViewOsc
@@ -2120,6 +2144,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview
@@ -2315,8 +2340,9 @@ pio=system.membus.master[4]
 
 [system.realview.mcc]
 type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.mcc.osc_clcd]
 type=RealViewOsc
@@ -2362,6 +2388,16 @@ position=0
 site=0
 voltage_domain=system.voltage_domain
 
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
index 9318c50111e7acd57d58fd967e4334e2f8e2f581..e34805b0d3387a4e1dc7b70def7b126afe852662 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
@@ -12,8 +12,6 @@ warn:         instruction 'mcr dccmvau' unimplemented
 warn:  instruction 'mcr icimvau' unimplemented
 warn:  instruction 'mcr bpiallis' unimplemented
 warn:  instruction 'mcr icialluis' unimplemented
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn:  instruction 'mcr dccimvac' unimplemented
 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -33,6 +31,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
@@ -40,21 +40,20 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10462, Bank: 2
+warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8288, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6918, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11135, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11139, Bank: 6
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[0]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10621, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11318, Bank: 7
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
@@ -64,11 +63,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[10], opc1[0], crm[4], opc2[3]
 warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
-warn: CP14 unimplemented crn[7], opc1[0], crm[12], opc2[1]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -79,14 +79,17 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn:  instruction 'mcr bpiall' unimplemented
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn:  instruction 'mcr dcisw' unimplemented
+warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
+warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
+warn:  instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0]
+warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -99,6 +102,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -107,14 +112,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 42b6a0fb049d52555b53005ac86783ccf027ad49..c8a56e9dc33f4a8a9235fe1c8569ada9f7d5feb3 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.823729                       # Nu
 sim_ticks                                2823728611500                       # Number of ticks simulated
 final_tick                               2823728611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 192143                       # Simulator instruction rate (inst/s)
-host_op_rate                                   233071                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4415299854                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 584992                       # Number of bytes of host memory used
-host_seconds                                   639.53                       # Real time elapsed on the host
+host_inst_rate                                 406612                       # Simulator instruction rate (inst/s)
+host_op_rate                                   493225                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9343639540                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 632204                       # Number of bytes of host memory used
+host_seconds                                   302.21                       # Real time elapsed on the host
 sim_insts                                   122881667                       # Number of instructions simulated
 sim_ops                                     149056790                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -534,7 +534,7 @@ system.cpu0.num_func_calls                    5787158                       # nu
 system.cpu0.num_conditional_control_insts      7357632                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                    58995481                       # number of integer instructions
 system.cpu0.num_fp_insts                         4380                       # number of float instructions
-system.cpu0.num_int_register_reads          108779991                       # number of times the integer registers were read
+system.cpu0.num_int_register_reads          108769217                       # number of times the integer registers were read
 system.cpu0.num_int_register_writes          41129875                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3339                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1042                       # number of times the floating registers were written
@@ -1292,7 +1292,7 @@ system.cpu1.num_func_calls                    1992181                       # nu
 system.cpu1.num_conditional_control_insts      2177842                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    18584422                       # number of integer instructions
 system.cpu1.num_fp_insts                         1582                       # number of float instructions
-system.cpu1.num_int_register_reads           34435383                       # number of times the integer registers were read
+system.cpu1.num_int_register_reads           34431709                       # number of times the integer registers were read
 system.cpu1.num_int_register_writes          13029372                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1129                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                454                       # number of times the floating registers were written
@@ -1852,7 +1852,7 @@ system.cpu3.rename.IQFullEvents               1185922                       # Nu
 system.cpu3.rename.LQFullEvents                108960                       # Number of times rename has blocked due to LQ full
 system.cpu3.rename.SQFullEvents               3941702                       # Number of times rename has blocked due to SQ full
 system.cpu3.rename.RenamedOperands           46859897                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            206328923                       # Number of register rename lookups that rename has made
+system.cpu3.rename.RenameLookups            206319121                       # Number of register rename lookups that rename has made
 system.cpu3.rename.int_rename_lookups        50493322                       # Number of integer rename lookups
 system.cpu3.rename.fp_rename_lookups             4028                       # Number of floating rename lookups
 system.cpu3.rename.CommittedMaps             39227152                       # Number of HB maps that are committed
@@ -1869,7 +1869,7 @@ system.cpu3.iq.iqNonSpecInstsAdded             518690                       # Nu
 system.cpu3.iq.iqInstsIssued                 41211343                       # Number of instructions issued
 system.cpu3.iq.iqSquashedInstsIssued            55539                       # Number of squashed instructions issued
 system.cpu3.iq.iqSquashedInstsExamined        6082671                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     14073441                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedOperandsExamined     14072351                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu3.iq.iqSquashedNonSpecRemoved         54569                       # Number of squashed non-spec instructions that were removed
 system.cpu3.iq.issued_per_cycle::samples     54325621                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::mean        0.758599                       # Number of insts issued each cycle
@@ -2091,7 +2091,7 @@ system.cpu3.fp_regfile_reads                    14550                       # nu
 system.cpu3.fp_regfile_writes                   12084                       # number of floating regfile writes
 system.cpu3.cc_regfile_reads                144202792                       # number of cc regfile reads
 system.cpu3.cc_regfile_writes                15932581                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads               74870960                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads               74868210                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                343753                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30152                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30152                       # Transaction distribution

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index 847b205be4630ae7cf8175bfea177560ba086efd..00e7e273901ad39fbfad17453a70ea073d1834c7 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -47,6 +47,8 @@ phys_addr_range_64=40
 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -199,11 +201,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu0.dcache]
 type=Cache
@@ -804,11 +813,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu1.dstage2_mmu]
 type=ArmStage2MMU
@@ -1339,14 +1355,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1373,6 +1389,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -1577,6 +1600,7 @@ pio=system.iobus.master[5]
 type=SubSystem
 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.dcc.osc_cpu]
 type=RealViewOsc
@@ -1769,6 +1793,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview
@@ -1964,8 +1989,9 @@ pio=system.membus.master[4]
 
 [system.realview.mcc]
 type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.mcc.osc_clcd]
 type=RealViewOsc
@@ -2011,6 +2037,16 @@ position=0
 site=0
 voltage_domain=system.voltage_domain
 
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
index d345b4b2db6158b04a6cb246193f94c2c46a2163..2c5672b0b290a3794fc9fb359527d7b4f9ad78e2 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
@@ -26,31 +26,38 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
 warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
+warn: CP14 unimplemented crn[1], opc1[4], crm[12], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
 warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
+warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
 warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmcr
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[6]
+warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[2]
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2]
 warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
-warn: CP14 unimplemented crn[3], opc1[0], crm[0], opc2[0]
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
-warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
+warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
 warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
+warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3]
+warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3]
 warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[0]
-warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
-warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[0]
-warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[1]
-warn: CP14 unimplemented crn[12], opc1[0], crm[0], opc2[3]
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[3]
 warn:  instruction 'mcr dcisw' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn:  instruction 'mcr bpiall' unimplemented
-warn: CP14 unimplemented crn[2], opc1[2], crm[4], opc2[1]
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 8140fab3341aa2797a2b5829eed9b16caed19a4f..3a095587738fdbc27acb5038237525c7b1f11f4b 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.804583                       # Nu
 sim_ticks                                2804582834000                       # Number of ticks simulated
 final_tick                               2804582834000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77550                       # Simulator instruction rate (inst/s)
-host_op_rate                                    94124                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1860425573                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 586788                       # Number of bytes of host memory used
-host_seconds                                  1507.50                       # Real time elapsed on the host
+host_inst_rate                                 167374                       # Simulator instruction rate (inst/s)
+host_op_rate                                   203147                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4015325540                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 633236                       # Number of bytes of host memory used
+host_seconds                                   698.47                       # Real time elapsed on the host
 sim_insts                                   116905819                       # Number of instructions simulated
 sim_ops                                     141891765                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -639,7 +639,7 @@ system.cpu0.rename.IQFullEvents               1036846                       # Nu
 system.cpu0.rename.LQFullEvents                275223                       # Number of times rename has blocked due to LQ full
 system.cpu0.rename.SQFullEvents               5569610                       # Number of times rename has blocked due to SQ full
 system.cpu0.rename.RenamedOperands           83235701                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            372792978                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RenameLookups            372775200                       # Number of register rename lookups that rename has made
 system.cpu0.rename.int_rename_lookups        90140763                       # Number of integer rename lookups
 system.cpu0.rename.fp_rename_lookups             7010                       # Number of floating rename lookups
 system.cpu0.rename.CommittedMaps             70379825                       # Number of HB maps that are committed
@@ -656,7 +656,7 @@ system.cpu0.iq.iqNonSpecInstsAdded            1057787                       # Nu
 system.cpu0.iq.iqInstsIssued                 74749052                       # Number of instructions issued
 system.cpu0.iq.iqSquashedInstsIssued            90659                       # Number of squashed instructions issued
 system.cpu0.iq.iqSquashedInstsExamined       10605329                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23154537                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedOperandsExamined     23152649                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.iq.iqSquashedNonSpecRemoved        112514                       # Number of squashed non-spec instructions that were removed
 system.cpu0.iq.issued_per_cycle::samples    103827961                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::mean        0.719932                       # Number of insts issued each cycle
@@ -878,7 +878,7 @@ system.cpu0.fp_regfile_reads                    17106                       # nu
 system.cpu0.fp_regfile_writes                   13230                       # number of floating regfile writes
 system.cpu0.cc_regfile_reads                262463335                       # number of cc regfile reads
 system.cpu0.cc_regfile_writes                27226302                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              143950430                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads              143945708                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                725062                       # number of misc regfile writes
 system.cpu0.dcache.tags.replacements           852281                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.984445                       # Cycle average of tags in use
@@ -1571,7 +1571,7 @@ system.cpu1.rename.IQFullEvents               1748729                       # Nu
 system.cpu1.rename.LQFullEvents                211009                       # Number of times rename has blocked due to LQ full
 system.cpu1.rename.SQFullEvents               4894541                       # Number of times rename has blocked due to SQ full
 system.cpu1.rename.RenamedOperands           89713841                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            398200824                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RenameLookups            398185196                       # Number of register rename lookups that rename has made
 system.cpu1.rename.int_rename_lookups        96380963                       # Number of integer rename lookups
 system.cpu1.rename.fp_rename_lookups             6166                       # Number of floating rename lookups
 system.cpu1.rename.CommittedMaps             76287775                       # Number of HB maps that are committed
@@ -1588,7 +1588,7 @@ system.cpu1.iq.iqNonSpecInstsAdded            1152123                       # Nu
 system.cpu1.iq.iqInstsIssued                 80030097                       # Number of instructions issued
 system.cpu1.iq.iqSquashedInstsIssued            91651                       # Number of squashed instructions issued
 system.cpu1.iq.iqSquashedInstsExamined       10961230                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     24701225                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedOperandsExamined     24699895                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu1.iq.iqSquashedNonSpecRemoved        103564                       # Number of squashed non-spec instructions that were removed
 system.cpu1.iq.issued_per_cycle::samples    107161169                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::mean        0.746820                       # Number of insts issued each cycle
@@ -1810,7 +1810,7 @@ system.cpu1.fp_regfile_reads                    16634                       # nu
 system.cpu1.fp_regfile_writes                   13036                       # number of floating regfile writes
 system.cpu1.cc_regfile_reads                280643076                       # number of cc regfile reads
 system.cpu1.cc_regfile_writes                29716175                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              149728966                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads              149724890                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                794523                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
index be51ba10daaa35d79dca9f58459b9e3311a66390..35469b90f144dc099f79691b7772d68625c76ec0 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
@@ -20,10 +20,11 @@ dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
+exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -46,6 +47,8 @@ phys_addr_range_64=40
 readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -145,7 +148,6 @@ clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=2
 is_read_only=false
 max_miss_count=0
@@ -223,7 +225,6 @@ clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=2
 is_read_only=true
 max_miss_count=0
@@ -553,11 +554,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu2.dstage2_mmu]
 type=ArmStage2MMU
@@ -1156,11 +1164,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu3.dstage2_mmu]
 type=ArmStage2MMU
@@ -1626,7 +1641,6 @@ clk_domain=system.clk_domain
 clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=false
 hit_latency=50
 is_read_only=false
 max_miss_count=0
@@ -1663,7 +1677,6 @@ clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=20
 is_read_only=false
 max_miss_count=0
@@ -1693,13 +1706,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1726,6 +1740,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -1930,6 +1951,7 @@ pio=system.iobus.master[5]
 type=SubSystem
 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.dcc.osc_cpu]
 type=RealViewOsc
@@ -2122,6 +2144,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview
@@ -2317,8 +2340,9 @@ pio=system.membus.master[4]
 
 [system.realview.mcc]
 type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.mcc.osc_clcd]
 type=RealViewOsc
@@ -2364,6 +2388,16 @@ position=0
 site=0
 voltage_domain=system.voltage_domain
 
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
@@ -2587,6 +2621,7 @@ clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+point_of_coherency=false
 response_latency=1
 snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
index 14afb57bcb0dfda12458859816b082c5c9f685ff..b0ba116d494dfa9f5080f4e437644520d46e9e5b 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
@@ -5,26 +5,24 @@ warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
 warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
 warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8890, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9681, Bank: 7
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9468, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9409, Bank: 2
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9956, Bank: 2
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8667, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12274, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12120, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -42,23 +40,35 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 11643, Bank: 2
+Command: 0, Timestamp: 6517, Bank: 3
 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11264, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8878, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12188, Bank: 4
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -109,10 +119,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -129,6 +135,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -137,8 +147,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -151,10 +159,48 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7601, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7443, Bank: 1
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5441, Bank: 7
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5583, Bank: 7
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5642, Bank: 7
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5744, Bank: 7
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5805, Bank: 7
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5897, Bank: 7
+WARNING: Bank is not active!
+Command: 1, Timestamp: 6007, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6564, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11135, Bank: 7
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -163,6 +209,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -177,32 +231,30 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6453, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: Bank is already active!
-Command: 0, Timestamp: 8188, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9018, Bank: 6
+Command: 0, Timestamp: 10204, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11838, Bank: 3
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -211,22 +263,28 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6477, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 7445, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7567, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -239,8 +297,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12028, Bank: 7
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -255,16 +311,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -273,34 +323,26 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6774, Bank: 7
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10642, Bank: 6
+Command: 0, Timestamp: 6448, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -309,14 +351,18 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 9126, Bank: 4
+Command: 0, Timestamp: 10284, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6534, Bank: 3
+WARNING: Bank is not active!
+Command: 1, Timestamp: 3928, Bank: 1
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -327,28 +373,16 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11016, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -365,6 +399,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -389,14 +427,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -407,10 +445,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7643, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -419,8 +461,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10843, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -431,6 +475,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6764, Bank: 7
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -439,12 +489,20 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8559, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7033, Bank: 5
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -455,12 +513,16 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7772, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8190, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9257, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -469,34 +531,26 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -509,18 +563,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10981, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -529,6 +585,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -541,12 +599,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -557,10 +609,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -575,22 +623,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9067, Bank: 2
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -603,10 +635,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -619,10 +647,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -639,8 +663,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10772, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -651,16 +673,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6808, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -671,20 +697,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10047, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -713,6 +741,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -729,6 +763,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -745,14 +787,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -765,16 +805,44 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is not active!
+Command: 1, Timestamp: 4731, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 4795, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 4818, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5308, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5494, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5524, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5619, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5650, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5683, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5714, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 5778, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 6025, Bank: 1
+WARNING: Bank is not active!
+Command: 1, Timestamp: 6210, Bank: 1
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7197, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8763, Bank: 2
+Command: 0, Timestamp: 6448, Bank: 1
 WARNING: Bank is already active!
-Command: 0, Timestamp: 8788, Bank: 6
+Command: 0, Timestamp: 6993, Bank: 2
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10548, Bank: 1
+Command: 0, Timestamp: 12168, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -787,6 +855,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -797,20 +869,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -835,12 +893,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -863,14 +915,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9949, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -879,8 +931,20 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -901,18 +965,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -921,10 +981,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -937,8 +1005,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -949,10 +1019,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7475, Bank: 3
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -963,16 +1029,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9111, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -981,10 +1045,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -993,12 +1053,26 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7906, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1015,6 +1089,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1035,14 +1115,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7611, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1055,6 +1131,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1063,8 +1141,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1077,20 +1153,16 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1099,12 +1171,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9985, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8266, Bank: 1
+Command: 0, Timestamp: 6595, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1119,8 +1189,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1145,10 +1213,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1165,8 +1229,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1177,6 +1239,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1185,54 +1249,70 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6480, Bank: 7
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 7
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6508, Bank: 1
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7192, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7939, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1241,6 +1321,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6642, Bank: 4
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -1263,10 +1347,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1279,14 +1359,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10183, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1303,10 +1391,18 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index d8c58ee0c949934a069d32723f11da0d6f9f6dfd..d7be73045cac10fdf7716b9fc872195a64f9a14e 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.316243                       # Nu
 sim_ticks                                51316242679000                       # Number of ticks simulated
 final_tick                               51316242679000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 361668                       # Simulator instruction rate (inst/s)
-host_op_rate                                   424976                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            21619129427                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 686216                       # Number of bytes of host memory used
-host_seconds                                  2373.65                       # Real time elapsed on the host
+host_inst_rate                                 408194                       # Simulator instruction rate (inst/s)
+host_op_rate                                   479646                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24400273917                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 732460                       # Number of bytes of host memory used
+host_seconds                                  2103.10                       # Real time elapsed on the host
 sim_insts                                   858473131                       # Number of instructions simulated
 sim_ops                                    1008744567                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -372,10 +372,10 @@ system.physmem_1.preEnergy                  539141625                       # En
 system.physmem_1.readEnergy                1669683600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy               1531975680                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           3312965298240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1172482833105                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29689600432500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34179780291750                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.615252                       # Core power per rank (mW)
+system.physmem_1.actBackEnergy           1172484635445                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29689595916750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34179777578340                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.615263                       # Core power per rank (mW)
 system.physmem_1.memoryStateTime::IDLE   48917806002648                       # Time in different power states
 system.physmem_1.memoryStateTime::REF    1693745040000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
index 7c4566f67ba9f7d2e028b50bc7c27cc58bda244a..e2578c2a46d1bc4f3f0dd9bca9b46c018cacbe7b 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
@@ -32,135 +32,135 @@
 [    0.000000] NR_IRQS:64 nr_irqs:64 0\r
 [    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
 [    0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[    0.000014] Console: colour dummy device 80x25\r
-[    0.000015] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[    0.000016] pid_max: default: 32768 minimum: 301\r
-[    0.000024] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000025] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000086] hw perfevents: no hardware support available\r
-[    1.060049] CPU1: failed to come online\r
-[    2.080100] CPU2: failed to come online\r
-[    3.100151] CPU3: failed to come online\r
-[    3.100153] Brought up 1 CPUs\r
-[    3.100153] SMP: Total of 1 processors activated.\r
-[    3.100180] devtmpfs: initialized\r
-[    3.100805] atomic64_test: passed\r
-[    3.100869] regulator-dummy: no parameters\r
-[    3.101131] NET: Registered protocol family 16\r
-[    3.101220] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[    3.101223] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[    3.101262] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[    3.101264] Serial: AMBA PL011 UART driver\r
-[    3.101385] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[    3.101407] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[    3.101978] console [ttyAMA0] enabled\r
-[    3.102041] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[    3.102067] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[    3.102093] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[    3.102118] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[    3.130359] 3V3: 3300 mV \r
-[    3.130380] vgaarb: loaded\r
-[    3.130421] SCSI subsystem initialized\r
-[    3.130492] libata version 3.00 loaded.\r
-[    3.130577] usbcore: registered new interface driver usbfs\r
-[    3.130605] usbcore: registered new interface driver hub\r
-[    3.130658] usbcore: registered new device driver usb\r
-[    3.130692] pps_core: LinuxPPS API ver. 1 registered\r
-[    3.130701] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[    3.130721] PTP clock support registered\r
-[    3.130886] Switched to clocksource arch_sys_counter\r
-[    3.131839] NET: Registered protocol family 2\r
-[    3.131931] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[    3.131947] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[    3.131964] TCP: Hash tables configured (established 2048 bind 2048)\r
-[    3.131979] TCP: reno registered\r
-[    3.131985] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.132028] NET: Registered protocol family 1\r
-[    3.132061] RPC: Registered named UNIX socket transport module.\r
-[    3.132071] RPC: Registered udp transport module.\r
-[    3.132079] RPC: Registered tcp transport module.\r
-[    3.132087] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[    3.132098] PCI: CLS 0 bytes, default 64\r
-[    3.132201] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[    3.132250] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[    3.133974] fuse init (API version 7.23)\r
-[    3.134030] msgmni has been set to 469\r
-[    3.136051] io scheduler noop registered\r
-[    3.136088] io scheduler cfq registered (default)\r
-[    3.136364] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[    3.136366] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]\r
-[    3.136367] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[    3.136369] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[    3.136370] pci_bus 0000:00: scanning bus\r
-[    3.136372] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[    3.136374] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[    3.136377] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.136394] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[    3.136396] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]\r
-[    3.136398] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]\r
-[    3.136399] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]\r
-[    3.136401] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]\r
-[    3.136403] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]\r
-[    3.136405] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.136422] pci_bus 0000:00: fixups for bus\r
-[    3.136423] pci_bus 0000:00: bus scan returning with max=00\r
-[    3.136425] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[    3.136430] pci 0000:00:00.0: fixup irq: got 33\r
-[    3.136431] pci 0000:00:00.0: assigning IRQ 33\r
-[    3.136434] pci 0000:00:01.0: fixup irq: got 34\r
-[    3.136435] pci 0000:00:01.0: assigning IRQ 34\r
-[    3.136437] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[    3.136439] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[    3.136441] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[    3.136442] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]\r
-[    3.136444] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]\r
-[    3.136458] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]\r
-[    3.136471] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]\r
-[    3.136484] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]\r
-[    3.137065] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[    3.137231] ata_piix 0000:00:01.0: version 2.13\r
-[    3.137233] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[    3.137238] ata_piix 0000:00:01.0: enabling bus mastering\r
-[    3.137427] scsi0 : ata_piix\r
-[    3.137561] scsi1 : ata_piix\r
-[    3.137617] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[    3.137630] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[    3.137788] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[    3.137801] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[    3.137820] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[    3.137832] e1000 0000:00:00.0: enabling bus mastering\r
-[    3.290888] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[    3.290890] ata1.00: 2096640 sectors, multi 0: LBA \r
-[    3.290896] ata1.00: configured for UDMA/33\r
-[    3.290913] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5\r
-[    3.290974] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[    3.290982] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[    3.290996] sd 0:0:0:0: [sda] Write Protect is off\r
-[    3.290997] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[    3.291004] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[    3.291057]  sda: sda1\r
-[    3.291119] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[    3.411182] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[    3.411197] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[    3.411227] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[    3.411238] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[    3.411269] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[    3.411282] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[    3.411405] usbcore: registered new interface driver usb-storage\r
-[    3.411475] mousedev: PS/2 mouse device common for all mice\r
-[    3.411653] usbcore: registered new interface driver usbhid\r
-[    3.411663] usbhid: USB HID core driver\r
-[    3.411687] TCP: cubic registered\r
-[    3.411694] NET: Registered protocol family 17\r
-\0[    3.411918] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[    3.411928] devtmpfs: mounted\r
-[    3.411936] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[    0.000027] Console: colour dummy device 80x25\r
+[    0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[    0.000032] pid_max: default: 32768 minimum: 301\r
+[    0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[    0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[    0.000177] hw perfevents: no hardware support available\r
+[    1.060045] CPU1: failed to come online\r
+[    2.080096] CPU2: failed to come online\r
+[    3.100147] CPU3: failed to come online\r
+[    3.100149] Brought up 1 CPUs\r
+[    3.100150] SMP: Total of 1 processors activated.\r
+[    3.100176] devtmpfs: initialized\r
+[    3.100784] atomic64_test: passed\r
+[    3.100838] regulator-dummy: no parameters\r
+[    3.101093] NET: Registered protocol family 16\r
+[    3.101177] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[    3.101181] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[    3.101220] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[    3.101221] Serial: AMBA PL011 UART driver\r
+[    3.101342] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[    3.101365] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[    3.101399] console [ttyAMA0] enabled\r
+[    3.101503] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[    3.101553] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[    3.101603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[    3.101649] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[    3.130355] 3V3: 3300 mV \r
+[    3.130376] vgaarb: loaded\r
+[    3.130417] SCSI subsystem initialized\r
+[    3.130486] libata version 3.00 loaded.\r
+[    3.130565] usbcore: registered new interface driver usbfs\r
+[    3.130591] usbcore: registered new interface driver hub\r
+[    3.130645] usbcore: registered new device driver usb\r
+[    3.130677] pps_core: LinuxPPS API ver. 1 registered\r
+[    3.130686] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[    3.130706] PTP clock support registered\r
+[    3.130853] Switched to clocksource arch_sys_counter\r
+[    3.131766] NET: Registered protocol family 2\r
+[    3.131853] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[    3.131874] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[    3.131900] TCP: Hash tables configured (established 2048 bind 2048)\r
+[    3.131914] TCP: reno registered\r
+[    3.131921] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[    3.131933] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[    3.131960] NET: Registered protocol family 1\r
+[    3.131995] RPC: Registered named UNIX socket transport module.\r
+[    3.132005] RPC: Registered udp transport module.\r
+[    3.132012] RPC: Registered tcp transport module.\r
+[    3.132020] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[    3.132032] PCI: CLS 0 bytes, default 64\r
+[    3.132126] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[    3.132190] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[    3.133863] fuse init (API version 7.23)\r
+[    3.133946] msgmni has been set to 469\r
+[    3.135911] io scheduler noop registered\r
+[    3.135957] io scheduler cfq registered (default)\r
+[    3.136166] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[    3.136178] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]\r
+[    3.136189] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[    3.136190] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[    3.136191] pci_bus 0000:00: scanning bus\r
+[    3.136194] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[    3.136196] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[    3.136199] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[    3.136215] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[    3.136217] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]\r
+[    3.136219] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]\r
+[    3.136221] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]\r
+[    3.136222] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]\r
+[    3.136224] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]\r
+[    3.136226] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[    3.136243] pci_bus 0000:00: fixups for bus\r
+[    3.136244] pci_bus 0000:00: bus scan returning with max=00\r
+[    3.136246] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[    3.136251] pci 0000:00:00.0: fixup irq: got 33\r
+[    3.136252] pci 0000:00:00.0: assigning IRQ 33\r
+[    3.136255] pci 0000:00:01.0: fixup irq: got 34\r
+[    3.136256] pci 0000:00:01.0: assigning IRQ 34\r
+[    3.136258] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[    3.136260] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[    3.136262] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[    3.136264] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]\r
+[    3.136265] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]\r
+[    3.136267] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]\r
+[    3.136269] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]\r
+[    3.136270] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]\r
+[    3.136757] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[    3.137006] ata_piix 0000:00:01.0: version 2.13\r
+[    3.137015] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[    3.137032] ata_piix 0000:00:01.0: enabling bus mastering\r
+[    3.137198] scsi0 : ata_piix\r
+[    3.137253] scsi1 : ata_piix\r
+[    3.137270] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[    3.137271] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[    3.137332] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[    3.137333] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[    3.137337] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[    3.137339] e1000 0000:00:00.0: enabling bus mastering\r
+[    3.290857] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[    3.290858] ata1.00: 2096640 sectors, multi 0: LBA \r
+[    3.290864] ata1.00: configured for UDMA/33\r
+[    3.290881] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5\r
+[    3.290942] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[    3.290950] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[    3.290964] sd 0:0:0:0: [sda] Write Protect is off\r
+[    3.290965] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[    3.290972] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[    3.291025]  sda: sda1\r
+[    3.291087] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[    3.411146] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[    3.411161] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[    3.411190] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[    3.411201] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[    3.411232] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[    3.411245] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[    3.411368] usbcore: registered new interface driver usb-storage\r
+[    3.411435] mousedev: PS/2 mouse device common for all mice\r
+[    3.411616] usbcore: registered new interface driver usbhid\r
+[    3.411625] usbhid: USB HID core driver\r
+[    3.411647] TCP: cubic registered\r
+[    3.411654] NET: Registered protocol family 17\r
+\0[    3.411868] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[    3.411878] devtmpfs: mounted\r
+[    3.411886] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
 \0\0\rINIT: \0version 2.88 booting\0\r\r
 \0Starting udev\r
-[    3.450190] udevd[607]: starting version 182\r
+[    3.450099] udevd[607]: starting version 182\r
 Starting Bootlog daemon: bootlogd.\r\r
-[    3.533187] random: dd urandom read with 19 bits of entropy available\r
+[    3.543144] random: dd urandom read with 19 bits of entropy available\r
 Populating dev cache\r\r
 net.ipv4.conf.default.rp_filter = 1\r\r
 net.ipv4.conf.all.rp_filter = 1\r\r
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
 \rINIT: Entering runlevel: 5\r\r\r
 Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[    3.671104] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[    3.681072] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
 Sending discover...\r\r
 Sending discover...\r\r
 Sending discover...\r\r

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 692f636a05dc362f09138b49632fef783a7dd26f..7fcb963937c7eea47e293f148e1b99b64327eb48 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.dcache]
 type=Cache

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
index df9319b88f9d6bc49b96b047ee05ac83bce89f56..d9d33c634c5c294ff74f137de631baf809d388ae 100755 (executable)
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 5203c92b4fac5ea49f2f80c9870305cbc0b2534d..1617c9a7a0e168044d937485110f00d8dbe6c809 100755 (executable)
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -26,4 +26,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 58178990500 because target called exit()
+Exiting @ tick 58199030500 because target called exit()

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 5fa1b74da4af360c57c123f0a15f83f484991712..d33c4ab3bd7fbedb736253fec1fda58378f86675 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.058199                       # Nu
 sim_ticks                                 58199030500                       # Number of ticks simulated
 final_tick                                58199030500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 101249                       # Simulator instruction rate (inst/s)
-host_op_rate                                   101754                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               65047265                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 487144                       # Number of bytes of host memory used
-host_seconds                                   894.72                       # Real time elapsed on the host
+host_inst_rate                                 218368                       # Simulator instruction rate (inst/s)
+host_op_rate                                   219455                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              140289424                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 534192                       # Number of bytes of host memory used
+host_seconds                                   414.85                       # Real time elapsed on the host
 sim_insts                                    90589799                       # Number of instructions simulated
 sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -453,7 +453,7 @@ system.cpu.rename.IQFullEvents                1144918                       # Nu
 system.cpu.rename.LQFullEvents                1526969                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                 486977                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands           129945519                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             483153288                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups             483152587                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        119447216                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               432                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
@@ -470,7 +470,7 @@ system.cpu.iq.iqNonSpecInstsAdded                8283                       # Nu
 system.cpu.iq.iqInstsIssued                 101366848                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued           1074801                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined        18634403                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41667299                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined     41667039                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             65                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     116345779                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         0.871255                       # Number of insts issued each cycle
@@ -691,7 +691,7 @@ system.cpu.fp_regfile_reads                        59                       # nu
 system.cpu.fp_regfile_writes                       96                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                 369004699                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                 58686555                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                28410220                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                28410103                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           5470634                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.784091                       # Cycle average of tags in use

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 85cb6a0331f922ade53c1b8036c68b9ab2a601aa..5bb4589de82dec9b043e73d51f996bfd8ef6cdf0 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.dcache]
 type=Cache

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
index eeb19437b98c6bbad157939202f57a80e860ec81..be90b03400be2301bb436755a42348408832fa2b 100755 (executable)
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index a4234efc55d118d3fda57649d0bfaf425770483b..b1e4c3523cf90ee255ab81d3fb4689727caedab2 100755 (executable)
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -70,4 +70,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 234067145000 because target called exit()
+Exiting @ tick 232864525000 because target called exit()

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index af9a3042abedca6255fc0c89fe620ca5f24b5b90..b5fc0a42afc66e89e0193fb90ffb9fdcbe0feff1 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.232865                       # Nu
 sim_ticks                                232864525000                       # Number of ticks simulated
 final_tick                               232864525000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 141001                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152754                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               64987909                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295860                       # Number of bytes of host memory used
-host_seconds                                  3583.20                       # Real time elapsed on the host
+host_inst_rate                                 230904                       # Simulator instruction rate (inst/s)
+host_op_rate                                   250150                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              106424359                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 342436                       # Number of bytes of host memory used
+host_seconds                                  2188.08                       # Real time elapsed on the host
 sim_insts                                   505234934                       # Number of instructions simulated
 sim_ops                                     547348155                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -474,7 +474,7 @@ system.cpu.rename.IQFullEvents                2510705                       # Nu
 system.cpu.rename.LQFullEvents                1794472                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                1920747                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands           827509638                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3000483863                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups            3000483792                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        718633951                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                88                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             654095674                       # Number of HB maps that are committed
@@ -491,7 +491,7 @@ system.cpu.iq.iqNonSpecInstsAdded             2979350                       # Nu
 system.cpu.iq.iqInstsIssued                 608926727                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued           5749477                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined       120399705                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    306541360                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined    306541324                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved           1718                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     465093244                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         1.309257                       # Number of insts issued each cycle
@@ -711,7 +711,7 @@ system.cpu.int_regfile_writes               327337405                       # nu
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.cc_regfile_reads                2166261838                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                376539611                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               217603205                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               217603177                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           2817145                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.627957                       # Cycle average of tags in use

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 7cd34eb9f1e6690f74e900e2e74a0dce3461b7d6..6807fa19b19782009ab354b1baa3d5795f5d5f24 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1a4f967129e21563141e10f3a4cd6b03e3aa3b92 100755 (executable)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1 @@
+warn: Sockets disabled, not accepting gdb connections

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index e4f30df65e37d4bb2eef3ecb8e1a3395ab4f88bd..cec661f192a290ad363b92b2af3c3451828d562f 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.279361                       # Nu
 sim_ticks                                279360903000                       # Number of ticks simulated
 final_tick                               279360903000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1080925                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1170785                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              596093333                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259884                       # Number of bytes of host memory used
-host_seconds                                   468.65                       # Real time elapsed on the host
+host_inst_rate                                2212896                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2396859                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1220336248                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304900                       # Number of bytes of host memory used
+host_seconds                                   228.92                       # Real time elapsed on the host
 sim_insts                                   506578818                       # Number of instructions simulated
 sim_ops                                     548692039                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -164,7 +164,7 @@ system.cpu.num_func_calls                    19311615                       # nu
 system.cpu.num_conditional_control_insts     90670594                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    448447005                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads           749023756                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           749023721                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          289993515                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index 46644e2cb4248d2909df3a02cf28efddd723ef18..f7f42e1944260a651bcb971c427d80de3140ab71 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1a4f967129e21563141e10f3a4cd6b03e3aa3b92 100755 (executable)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1 @@
+warn: Sockets disabled, not accepting gdb connections

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index b0856dd07af9c38ae59ce35155d8f6926277ea05..925783e416b8318c52ad9b8f97b9bf4320bf089f 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.708539                       # Nu
 sim_ticks                                708539449500                       # Number of ticks simulated
 final_tick                               708539449500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 670051                       # Simulator instruction rate (inst/s)
-host_op_rate                                   725636                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              940143705                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269876                       # Number of bytes of host memory used
-host_seconds                                   753.65                       # Real time elapsed on the host
+host_inst_rate                                1440714                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1560229                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2021455048                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314896                       # Number of bytes of host memory used
+host_seconds                                   350.51                       # Real time elapsed on the host
 sim_insts                                   504984064                       # Number of instructions simulated
 sim_ops                                     546875315                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -165,7 +165,7 @@ system.cpu.num_func_calls                    19311615                       # nu
 system.cpu.num_conditional_control_insts     90670594                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    448447005                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads           748339662                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           748339627                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          289993515                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index d1a772d56011b5185181f0c23ff7bf4834c0277a..a48b863896ed3a5bb12bcbd26e84e1a560003739 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.dcache]
 type=Cache

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
index 0c3e31a9cbda03d1be19fb96aee3b16d99927117..613c6a6b709bd26e827ee19ed8e3de8750bf8ab8 100755 (executable)
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
@@ -1,4 +1,5 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index 578b6774f3d67e503cd8307d69bd6340d4972c85..57226860760264d2fe681dade694cbb8fd6acf27 100755 (executable)
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -16,4 +16,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.110000
-Exiting @ tick 116576497500 because target called exit()
+Exiting @ tick 111753553500 because target called exit()

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index f9a8145d7595d007b5a37dbb7d597f2a06f2dd94..14b00e16f7d8f9e47b7af9e9b1bd4b5779b4085b 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.111754                       # Nu
 sim_ticks                                111753553500                       # Number of ticks simulated
 final_tick                               111753553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 118120                       # Simulator instruction rate (inst/s)
-host_op_rate                                   141817                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               48346375                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 287716                       # Number of bytes of host memory used
-host_seconds                                  2311.52                       # Real time elapsed on the host
+host_inst_rate                                 210028                       # Simulator instruction rate (inst/s)
+host_op_rate                                   252162                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               85964130                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 334160                       # Number of bytes of host memory used
+host_seconds                                  1300.00                       # Real time elapsed on the host
 sim_insts                                   273037220                       # Number of instructions simulated
 sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -436,7 +436,7 @@ system.cpu.rename.LQFullEvents                7483674                       # Nu
 system.cpu.rename.SQFullEvents               23725025                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.FullRegisterEvents          3279176                       # Number of times there has been no free registers
 system.cpu.rename.RenamedOperands           394880845                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2465405554                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups            2218133140                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        335914250                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups         192916662                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             372230051                       # Number of HB maps that are committed
@@ -453,7 +453,7 @@ system.cpu.iq.iqNonSpecInstsAdded               22608                       # Nu
 system.cpu.iq.iqInstsIssued                 339469619                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued            966789                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined        15494628                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     40533427                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined     37288530                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            488                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     222582301                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         1.525142                       # Number of insts issued each cycle
@@ -674,7 +674,7 @@ system.cpu.fp_regfile_reads                 186641875                       # nu
 system.cpu.fp_regfile_writes                131668024                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                1279432977                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                 80060950                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1175447336                       # number of misc regfile reads
+system.cpu.misc_regfile_reads              1056766060                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           1542955                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.836799                       # Cycle average of tags in use

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index 4e3e7fbd7e2f0d24fb7b5221e4802740f1fda792..f27ac4466d27a74b100928b102f7e77f4e473d91 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
+exit_on_work_items=false
 init_param=0
 kernel=
 kernel_addr_check=true
@@ -24,9 +25,12 @@ mem_mode=atomic
 mem_ranges=
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -130,6 +134,7 @@ eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+decoderFlavour=Generic
 eventq_index=0
 fpsid=1090793632
 id_aa64afr0_el1=0
@@ -248,6 +253,7 @@ clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+point_of_coherency=true
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 4a706dd9236e100cc1bf12855dc424a79cadaf39..ae8086be1da02431fda14767c756e89441303978 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.201717                       # Nu
 sim_ticks                                201717314000                       # Number of ticks simulated
 final_tick                               201717314000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 686314                       # Simulator instruction rate (inst/s)
-host_op_rate                                   823996                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              507041348                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264028                       # Number of bytes of host memory used
-host_seconds                                   397.83                       # Real time elapsed on the host
+host_inst_rate                                1495302                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1795276                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1104713261                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309028                       # Number of bytes of host memory used
+host_seconds                                   182.60                       # Real time elapsed on the host
 sim_insts                                   273037595                       # Number of instructions simulated
 sim_ops                                     327811950                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -164,7 +164,7 @@ system.cpu.num_func_calls                    12448615                       # nu
 system.cpu.num_conditional_control_insts     15799338                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    258331481                       # number of integer instructions
 system.cpu.num_fp_insts                     114216705                       # number of float instructions
-system.cpu.num_int_register_reads          1174407516                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           938030601                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          162499657                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index 2a5bb373220d80c4740ace6ff2a1c406f461d442..72dade1ff45cab0807aeff3e5ff0597bc3c130ac 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
index 7e050de514d6acdb0f08aa58c2b04fed9b5702d8..a25196116328f6cd9f295612ee295e3f352ca144 100755 (executable)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
 getting pixel output filename pixels_out.cook
 opening control file chair.control.cook
 opening camera file chair.camera

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 3e9613199a4f88afe32497eebd2035d4360d70b1..fadffed887edd40c28c39186fcd8f7d99a60331a 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.517291                       # Nu
 sim_ticks                                517291025500                       # Number of ticks simulated
 final_tick                               517291025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 454164                       # Simulator instruction rate (inst/s)
-host_op_rate                                   545241                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              861389873                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 274016                       # Number of bytes of host memory used
-host_seconds                                   600.53                       # Real time elapsed on the host
+host_inst_rate                                 977708                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1173775                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1854370201                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319164                       # Number of bytes of host memory used
+host_seconds                                   278.96                       # Real time elapsed on the host
 sim_insts                                   272739286                       # Number of instructions simulated
 sim_ops                                     327433744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -158,7 +158,7 @@ system.cpu.num_func_calls                    12448615                       # nu
 system.cpu.num_conditional_control_insts     15799349                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    258331537                       # number of integer instructions
 system.cpu.num_fp_insts                     114216705                       # number of float instructions
-system.cpu.num_int_register_reads          1215888421                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           979511506                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          162499693                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index b3e0aa264abcca85906f36b68d3b9c6fae88f93e..1c8fe2c03f8a78376e4b030f37d01a5506e0baea 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.dcache]
 type=Cache

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
index 04ac820567196c57869b6094cfae626607375f43..2e6ab1e7e6fc5dfc0499070da04d6e1eae3b9ea4 100755 (executable)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
 warn: fcntl64(3, 2) passed through to host

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index b72d2648e137c2d58f6a852e46165eb89b6f9572..17f97ea4254eeaf65bd7e309a31f6e90928c77d2 100755 (executable)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 452563515000 because target called exit()
+Exiting @ tick 326731324000 because target called exit()

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 2bcb8651d46e6a368c8fee558dad384e88984bd2..a4f9b9a0fde0bd65f8731e18ba6f6a80fc87c781 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.326731                       # Nu
 sim_ticks                                326731324000                       # Number of ticks simulated
 final_tick                               326731324000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 120212                       # Simulator instruction rate (inst/s)
-host_op_rate                                   147997                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61308199                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 272964                       # Number of bytes of host memory used
-host_seconds                                  5329.33                       # Real time elapsed on the host
+host_inst_rate                                 188423                       # Simulator instruction rate (inst/s)
+host_op_rate                                   231974                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               96095829                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319396                       # Number of bytes of host memory used
+host_seconds                                  3400.06                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -476,7 +476,7 @@ system.cpu.rename.IQFullEvents                2218724                       # Nu
 system.cpu.rename.LQFullEvents               49336465                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                 494906                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands           980929615                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4376071754                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups            4317999600                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups       1001832293                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups          34457071                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
@@ -493,7 +493,7 @@ system.cpu.iq.iqNonSpecInstsAdded               12579                       # Nu
 system.cpu.iq.iqInstsIssued                 860025252                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued           9216952                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined       111114003                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    248251839                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined    244402361                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            425                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     653119493                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         1.316796                       # Number of insts issued each cycle
@@ -714,7 +714,7 @@ system.cpu.fp_regfile_reads                  30616061                       # nu
 system.cpu.fp_regfile_writes                 22959483                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                3322370942                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                369203387                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               632347849                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               606830949                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           2756452                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.912722                       # Cycle average of tags in use

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index af71e081d30019f175849fbf2d6b23dd27653eb2..844cbdea4282fa75b4e66ad7ff5db16df318aa9a 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
+exit_on_work_items=false
 init_param=0
 kernel=
 kernel_addr_check=true
@@ -24,9 +25,12 @@ mem_mode=atomic
 mem_ranges=
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -130,6 +134,7 @@ eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+decoderFlavour=Generic
 eventq_index=0
 fpsid=1090793632
 id_aa64afr0_el1=0
@@ -248,6 +253,7 @@ clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+point_of_coherency=true
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 2146f54c477081bba8da5fc276564ea4a157cb64..1251990c8eee83944725d8df41f92d73045626ea 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.395727                       # Nu
 sim_ticks                                395726778500                       # Number of ticks simulated
 final_tick                               395726778500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 878754                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1081862                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              542799023                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264636                       # Number of bytes of host memory used
-host_seconds                                   729.05                       # Real time elapsed on the host
+host_inst_rate                                1843468                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2269552                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1138694237                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309656                       # Number of bytes of host memory used
+host_seconds                                   347.53                       # Real time elapsed on the host
 sim_insts                                   640654411                       # Number of instructions simulated
 sim_ops                                     788730070                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -164,7 +164,7 @@ system.cpu.num_func_calls                    37261296                       # nu
 system.cpu.num_conditional_control_insts     91575866                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    682251400                       # number of integer instructions
 system.cpu.num_fp_insts                      24239771                       # number of float instructions
-system.cpu.num_int_register_reads          1320162254                       # number of times the integer registers were read
+system.cpu.num_int_register_reads          1268495038                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          468423268                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads             28064643                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes            21684311                       # number of times the floating registers were written

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 261f6c290bcd03b2312a9647cbd891b9c2d49f4f..b8d9750e5123b33dcb8e4c9c593bb2d184221094 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -15,6 +15,7 @@ boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
+exit_on_work_items=false
 init_param=0
 kernel=
 kernel_addr_check=true
@@ -24,9 +25,12 @@ mem_mode=timing
 mem_ranges=
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -85,9 +89,9 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=2
 is_read_only=false
 max_miss_count=0
@@ -101,6 +105,7 @@ system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
@@ -161,9 +166,9 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=2
 is_read_only=true
 max_miss_count=0
@@ -177,6 +182,7 @@ system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
@@ -196,6 +202,7 @@ eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+decoderFlavour=Generic
 eventq_index=0
 fpsid=1090793632
 id_aa64afr0_el1=0
@@ -271,9 +278,9 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=20
 is_read_only=false
 max_miss_count=0
@@ -287,6 +294,7 @@ system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
@@ -302,12 +310,14 @@ size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+point_of_coherency=false
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -315,6 +325,13 @@ width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.cpu.tracer]
 type=ExeTracer
 eventq_index=0
@@ -364,6 +381,7 @@ clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+point_of_coherency=true
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index 1fa1e0e5c3422e1b5f0cf95cfb13656e0c6f5b47..918fa3cf1d4264c0bb064814d3966c88dfd7de1c 100755 (executable)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
 2000: 2845746745
 1000: 2068042552
 0: 290958364
-Exiting @ tick 1043722398500 because target called exit()
+Exiting @ tick 1045756396500 because target called exit()

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index a634350c68b34d343944b35e0169ea6abd1d46b3..0aed4ec36ca73c717c2877992cdebade17e1fdc5 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.045756                       # Nu
 sim_ticks                                1045756396500                       # Number of ticks simulated
 final_tick                               1045756396500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 554447                       # Simulator instruction rate (inst/s)
-host_op_rate                                   681172                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              906860836                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273604                       # Number of bytes of host memory used
-host_seconds                                  1153.16                       # Real time elapsed on the host
+host_inst_rate                                1156934                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1421363                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1892295085                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319640                       # Number of bytes of host memory used
+host_seconds                                   552.64                       # Real time elapsed on the host
 sim_insts                                   639366787                       # Number of instructions simulated
 sim_ops                                     785501035                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -165,7 +165,7 @@ system.cpu.num_func_calls                    37261296                       # nu
 system.cpu.num_conditional_control_insts     91575866                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    682251400                       # number of integer instructions
 system.cpu.num_fp_insts                      24239771                       # number of float instructions
-system.cpu.num_int_register_reads          1323974869                       # number of times the integer registers were read
+system.cpu.num_int_register_reads          1272307653                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          468423268                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads             28064643                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes            21684311                       # number of times the floating registers were written

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 20ac0edc37295313b519615e6d6c79921fdf13b5..cbb778c283e345307fc7151be8265d942529293c 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.dcache]
 type=Cache

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
index f9e2ef3b23da7d227b91910c77804d262fc14ee9..341b479f785542f5c2bed7598ad1c56ad8887a02 100755 (executable)
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
@@ -1 +1,2 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index afe952dfbbd50f0f5e60fac8f7af4b11497e9902..dab41dff0f193656a1a2e1d79c6e85f52f937ae5 100755 (executable)
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -11,4 +11,4 @@ command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/li
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 33708718000 because target called exit()
+Exiting @ tick 33524756000 because target called exit()

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 285c58345cd4dee3e9db70dcf84ac5ab4860d56f..f186d41b5a308163e0d590b2b3c8e40202f0d48b 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.033525                       # Nu
 sim_ticks                                 33524756000                       # Number of ticks simulated
 final_tick                                33524756000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 102958                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131671                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               48677985                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277880                       # Number of bytes of host memory used
-host_seconds                                   688.70                       # Real time elapsed on the host
+host_inst_rate                                 201547                       # Simulator instruction rate (inst/s)
+host_op_rate                                   257754                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               95290096                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 324320                       # Number of bytes of host memory used
+host_seconds                                   351.82                       # Real time elapsed on the host
 sim_insts                                    70907652                       # Number of instructions simulated
 sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -463,7 +463,7 @@ system.cpu.rename.IQFullEvents                  69359                       # Nu
 system.cpu.rename.LQFullEvents                4461482                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                5194138                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands           103316551                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             453881397                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups             453880702                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        114363596                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               706                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              93629369                       # Number of HB maps that are committed
@@ -480,7 +480,7 @@ system.cpu.iq.iqNonSpecInstsAdded               34812                       # Nu
 system.cpu.iq.iqInstsIssued                  94518121                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued            609879                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined         6819583                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     18149075                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined     18148637                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved           1026                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples      66043378                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         1.431152                       # Number of insts issued each cycle
@@ -701,7 +701,7 @@ system.cpu.fp_regfile_reads                        48                       # nu
 system.cpu.fp_regfile_writes                       42                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                 345209533                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                 38766867                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                44112758                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                44112661                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements            486293                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           510.756058                       # Cycle average of tags in use

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 6544ce2444ac0f409c4438375c7e2b78fec996af..540dec5abdc5ca46cab1e4586c75fc2a2533974c 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.dcache]
 type=Cache

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
index eeb19437b98c6bbad157939202f57a80e860ec81..be90b03400be2301bb436755a42348408832fa2b 100755 (executable)
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index dc097b928a5864d326c23c4aeb0486aff052a175..77417a942594eab0243e17c00b137587256c01cb 100755 (executable)
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -27,4 +27,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 767851412000 because target called exit()
+Exiting @ tick 767803843500 because target called exit()

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 94c50de3e7a2034d65adcace41577620c4e02e03..d2e653fdf0b60fb858ca35ad9952cfedce46020c 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.767804                       # Nu
 sim_ticks                                767803843500                       # Number of ticks simulated
 final_tick                               767803843500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 196848                       # Simulator instruction rate (inst/s)
-host_op_rate                                   212074                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               97853290                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309012                       # Number of bytes of host memory used
-host_seconds                                  7846.48                       # Real time elapsed on the host
+host_inst_rate                                 232866                       # Simulator instruction rate (inst/s)
+host_op_rate                                   250878                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              115757951                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 355612                       # Number of bytes of host memory used
+host_seconds                                  6632.84                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -478,7 +478,7 @@ system.cpu.rename.IQFullEvents                 126625                       # Nu
 system.cpu.rename.LQFullEvents                1588286                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents               25069373                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands          1985943496                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            9128568325                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups            9128568020                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups       2432995559                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               145                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
@@ -495,7 +495,7 @@ system.cpu.iq.iqNonSpecInstsAdded                 231                       # Nu
 system.cpu.iq.iqInstsIssued                1857492479                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued          13497229                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined       284014957                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    647584155                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined    647584065                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             61                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples    1535531474                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         1.209674                       # Number of insts issued each cycle
@@ -716,7 +716,7 @@ system.cpu.fp_regfile_reads                        42                       # nu
 system.cpu.fp_regfile_writes                       54                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                6965778765                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                551854660                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               675853693                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               675853616                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements          17003710                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.964650                       # Cycle average of tags in use

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index dce12b6b3cdcd9d9d183896bff7e066bbefd60c9..1b535494d1899b73c5ea30bbb4c8805972e5d93d 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
+exit_on_work_items=false
 init_param=0
 kernel=
 kernel_addr_check=true
@@ -24,9 +25,12 @@ mem_mode=atomic
 mem_ranges=
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -130,6 +134,7 @@ eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+decoderFlavour=Generic
 eventq_index=0
 fpsid=1090793632
 id_aa64afr0_el1=0
@@ -248,6 +253,7 @@ clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+point_of_coherency=true
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index e972d8df423e6644d901b2ce726e2bc59e51a06f..6fb821b07251517e4f6ed2cf48455e6874389d71 100755 (executable)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -6,7 +6,6 @@ gem5 started Jan 23 2014 18:13:20
 gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x571a380
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
 Loading Input Data
@@ -25,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 861538200000 because target called exit()
+Exiting @ tick 832017490500 because target called exit()

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index f7caf50c2c00aecdc5ebe7e75fa4a4da4f30fde4..cac059bf6e47b74a2ff6987282768727d5ee9566 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.832017                       # Nu
 sim_ticks                                832017490500                       # Number of ticks simulated
 final_tick                               832017490500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1043463                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1124173                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              562087533                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256656                       # Number of bytes of host memory used
-host_seconds                                  1480.23                       # Real time elapsed on the host
+host_inst_rate                                2181717                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2350469                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1175236125                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 301652                       # Number of bytes of host memory used
+host_seconds                                   707.96                       # Real time elapsed on the host
 sim_insts                                  1544563042                       # Number of instructions simulated
 sim_ops                                    1664032434                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -164,7 +164,7 @@ system.cpu.num_func_calls                    27330256                       # nu
 system.cpu.num_conditional_control_insts    167612489                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1477900422                       # number of integer instructions
 system.cpu.num_fp_insts                            36                       # number of float instructions
-system.cpu.num_int_register_reads          2605402942                       # number of times the integer registers were read
+system.cpu.num_int_register_reads          2605402867                       # number of times the integer registers were read
 system.cpu.num_int_register_writes         1125475224                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 8ed495e8cb21fc30ed39dbac378ea21c741fc630..d42bc7142fae1119015318d13616e33622c51c03 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -15,6 +15,7 @@ boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
+exit_on_work_items=false
 init_param=0
 kernel=
 kernel_addr_check=true
@@ -24,9 +25,12 @@ mem_mode=timing
 mem_ranges=
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -85,9 +89,9 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=2
 is_read_only=false
 max_miss_count=0
@@ -101,6 +105,7 @@ system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
@@ -161,9 +166,9 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=2
 is_read_only=true
 max_miss_count=0
@@ -177,6 +182,7 @@ system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
@@ -196,6 +202,7 @@ eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+decoderFlavour=Generic
 eventq_index=0
 fpsid=1090793632
 id_aa64afr0_el1=0
@@ -271,9 +278,9 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
 hit_latency=20
 is_read_only=false
 max_miss_count=0
@@ -287,6 +294,7 @@ system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
@@ -302,12 +310,14 @@ size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
+point_of_coherency=false
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -315,6 +325,13 @@ width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.cpu.tracer]
 type=ExeTracer
 eventq_index=0
@@ -364,6 +381,7 @@ clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
+point_of_coherency=true
 response_latency=2
 snoop_filter=Null
 snoop_response_latency=4

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index 4d71ca6660043e63a43e2f221e1c6e99542b82cd..8064c269e57b3c9dfb0811a1e81f179c2ab055ab 100755 (executable)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
@@ -6,7 +8,6 @@ gem5 started Jan 23 2014 18:15:41
 gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
-      0: system.cpu.isa: ISA system set to: 0 0x5333d00
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
 Loading Input Data
@@ -25,4 +26,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2391205115000 because target called exit()
+Exiting @ tick 2377029670500 because target called exit()

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 6f79ed44ac66cb9d4345e5c0e270a2326262d684..e1d79bb9d039d2de7dcc788ed507ceef3b934a4b 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.377030                       # Nu
 sim_ticks                                2377029670500                       # Number of ticks simulated
 final_tick                               2377029670500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 651336                       # Simulator instruction rate (inst/s)
-host_op_rate                                   701905                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1006163929                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265624                       # Number of bytes of host memory used
-host_seconds                                  2362.47                       # Real time elapsed on the host
+host_inst_rate                                1359798                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1465373                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2100575394                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 311664                       # Number of bytes of host memory used
+host_seconds                                  1131.61                       # Real time elapsed on the host
 sim_insts                                  1538759602                       # Number of instructions simulated
 sim_ops                                    1658228915                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -165,7 +165,7 @@ system.cpu.num_func_calls                    27330256                       # nu
 system.cpu.num_conditional_control_insts    167612489                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1477900422                       # number of integer instructions
 system.cpu.num_fp_insts                            36                       # number of float instructions
-system.cpu.num_int_register_reads          2601860372                       # number of times the integer registers were read
+system.cpu.num_int_register_reads          2601860297                       # number of times the integer registers were read
 system.cpu.num_int_register_writes         1125475224                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 3195ac533dab80447a70f5e7fb5fd61436420c37..71957ae5a78f3a1d6e3b04b98daf587ba3108e46 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -29,6 +29,8 @@ multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -147,8 +149,15 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 numThreads=1
+useIndirect=true
 
 [system.cpu.dcache]
 type=Cache

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
index f9e2ef3b23da7d227b91910c77804d262fc14ee9..341b479f785542f5c2bed7598ad1c56ad8887a02 100755 (executable)
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
@@ -1 +1,2 @@
 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index e145846b209504574a10c2d0c2849b21294b9ce9..00456d1c3355ed4fb04affd3a25ca7dd4ef6437a 100755 (executable)
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -8,8 +8,6 @@ gem5 started Mar 15 2016 20:14:36
 gem5 executing on dinar2c11, pid 10702
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
 
-Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -26,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 85490431000 because target called exit()
+122 123 124 Exiting @ tick 84937723500 because target called exit()

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 5e6d9ee12e6b1001691ce32758772620e7eae645..a41b2e1943838d00d64fdedd561e485cd0e11397 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.084938                       # Nu
 sim_ticks                                 84937723500                       # Number of ticks simulated
 final_tick                                84937723500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  96546                       # Simulator instruction rate (inst/s)
-host_op_rate                                   101775                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47592642                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 268276                       # Number of bytes of host memory used
-host_seconds                                  1784.68                       # Real time elapsed on the host
+host_inst_rate                                 205804                       # Simulator instruction rate (inst/s)
+host_op_rate                                   216952                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              101452217                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314712                       # Number of bytes of host memory used
+host_seconds                                   837.22                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -436,7 +436,7 @@ system.cpu.rename.LQFullEvents                2280960                       # Nu
 system.cpu.rename.SQFullEvents                  36243                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.FullRegisterEvents            27083                       # Number of times there has been no free registers
 system.cpu.rename.RenamedOperands           481449871                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1191735135                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups            1187780717                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        296461789                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups           3004325                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
@@ -453,7 +453,7 @@ system.cpu.iq.iqNonSpecInstsAdded               45955                       # Nu
 system.cpu.iq.iqInstsIssued                 214411803                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued           5187874                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined        82208585                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    217092419                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined    216955908                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            739                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     169120520                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         1.267805                       # Number of insts issued each cycle
@@ -674,7 +674,7 @@ system.cpu.fp_regfile_reads                   2904222                       # nu
 system.cpu.fp_regfile_writes                  2441435                       # number of floating regfile writes
 system.cpu.cc_regfile_reads                 708194084                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                229512691                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                59249203                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                57440840                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements             72581                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.413915                       # Cycle average of tags in use

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
index 59c5ae050fcce93829b926518f6f4bb1d4958d5e..bf0fe93f022dd738a573b21ca4d5bdc0fe739217 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -830,6 +830,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
index f56eeb54981b342aa0ee65e502c1c6ba800f30fa..6078006ecfd2889eee239d0ad05b4b4263278856 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
@@ -67,7 +67,7 @@
         "thermal_model": null, 
         "phys_addr_range_64": 40, 
         "work_begin_exit_count": 0, 
-        "have_lpae": false, 
+        "have_lpae": true, 
         "cxx_class": "LinuxArmSystem", 
         "load_offset": 2147483648, 
         "vncserver": {
@@ -338,6 +338,7 @@
                 "type": "GenericTimer"
             }, 
             "gic": {
+                "gem5_extensions": true, 
                 "it_lines": 128, 
                 "name": "gic", 
                 "dist_addr": 738201600, 

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
index a1b437e07b500177cc4ce8f72f3e4ae29443a39b..f04e243f9ad3fc40d014985ae556d064fa8138df 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783855                       # Nu
 sim_ticks                                2783854535000                       # Number of ticks simulated
 final_tick                               2783854535000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 787133                       # Simulator instruction rate (inst/s)
-host_op_rate                                   958208                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            15348024787                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 576068                       # Number of bytes of host memory used
-host_seconds                                   181.38                       # Real time elapsed on the host
+host_inst_rate                                1770003                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2154695                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            34512663529                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 623244                       # Number of bytes of host memory used
+host_seconds                                    80.66                       # Real time elapsed on the host
 sim_insts                                   142771651                       # Number of instructions simulated
 sim_ops                                     173801592                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -219,7 +219,7 @@ system.cpu.num_func_calls                    16873962                       # nu
 system.cpu.num_conditional_control_insts     18730275                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    153161279                       # number of integer instructions
 system.cpu.num_fp_insts                         11484                       # number of float instructions
-system.cpu.num_int_register_reads           285057575                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           285030145                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          107178468                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 010d82106740bc4748538b9032f21cc35dc68cd6..1a31153e32b2565a488514cb0b5e0c8abfd82dba 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -841,14 +841,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -875,6 +875,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
@@ -1208,6 +1215,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index fc8f06b10b2317dac88702a1ed1b6c84a28923d4..95bb5652cad549f7909f89741a9b490804ddcbba 100755 (executable)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
@@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2802894699500 because m5_exit instruction encountered
+Exiting @ tick 2802882797500 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 317518f92fda58804d3210dbda9cc0865ba1e82a..1b60b638204513dbddd406f19cecbb7ba6094ef9 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.802883                       # Nu
 sim_ticks                                2802882797500                       # Number of ticks simulated
 final_tick                               2802882797500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 748827                       # Simulator instruction rate (inst/s)
-host_op_rate                                   912434                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14294755935                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 590384                       # Number of bytes of host memory used
-host_seconds                                   196.08                       # Real time elapsed on the host
+host_inst_rate                                1600792                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1950541                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            30558377305                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 639316                       # Number of bytes of host memory used
+host_seconds                                    91.72                       # Real time elapsed on the host
 sim_insts                                   146828219                       # Number of instructions simulated
 sim_ops                                     178907974                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -238,7 +238,7 @@ system.cpu0.num_func_calls                    8000241                       # nu
 system.cpu0.num_conditional_control_insts     13204192                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                   100762477                       # number of integer instructions
 system.cpu0.num_fp_insts                         9755                       # number of float instructions
-system.cpu0.num_int_register_reads          182456959                       # number of times the integer registers were read
+system.cpu0.num_int_register_reads          182433257                       # number of times the integer registers were read
 system.cpu0.num_int_register_writes          69135397                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
@@ -742,7 +742,7 @@ system.cpu1.num_func_calls                    9170873                       # nu
 system.cpu1.num_conditional_control_insts      5967115                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    56984416                       # number of integer instructions
 system.cpu1.num_fp_insts                         1792                       # number of float instructions
-system.cpu1.num_int_register_reads          110675031                       # number of times the integer registers were read
+system.cpu1.num_int_register_reads          110669758                       # number of times the integer registers were read
 system.cpu1.num_int_register_writes          41298494                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 59c5ae050fcce93829b926518f6f4bb1d4958d5e..bf0fe93f022dd738a573b21ca4d5bdc0fe739217 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -830,6 +830,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 3e281e6997c67a0427c0dd3ef028a0bcd64e4621..a7a9257247fd48af3f58b737d2362b889e8ac7ab 100755 (executable)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
@@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2783867052000 because m5_exit instruction encountered
+Exiting @ tick 2783854535000 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 422d7eb7f3a8341a61804ef2a4ec963c70b7d8b4..2c5a2e9446b59a12e650dff1de496a4ef25ee82e 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783855                       # Nu
 sim_ticks                                2783854535000                       # Number of ticks simulated
 final_tick                               2783854535000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 766060                       # Simulator instruction rate (inst/s)
-host_op_rate                                   932555                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14937129777                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 573732                       # Number of bytes of host memory used
-host_seconds                                   186.37                       # Real time elapsed on the host
+host_inst_rate                                1638061                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1994077                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31939974807                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 619068                       # Number of bytes of host memory used
+host_seconds                                    87.16                       # Real time elapsed on the host
 sim_insts                                   142771651                       # Number of instructions simulated
 sim_ops                                     173801592                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -219,7 +219,7 @@ system.cpu.num_func_calls                    16873962                       # nu
 system.cpu.num_conditional_control_insts     18730275                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    153161279                       # number of integer instructions
 system.cpu.num_fp_insts                         11484                       # number of float instructions
-system.cpu.num_int_register_reads           285057575                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           285030145                       # number of times the integer registers were read
 system.cpu.num_int_register_writes          107178468                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 5946c71cf1c731ea7febe9bec63bc180b70386af..f3f336a4e021bd1abc44b642ab60a84f41e9203a 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -833,14 +833,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -867,6 +867,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -1264,6 +1271,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index b8451630070caba1a1f34c2c81740dad75361dad..7be0675035d2b478d67a99d076cdbaf26ae011b8 100755 (executable)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
@@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2871850306000 because m5_exit instruction encountered
+Exiting @ tick 2869788970000 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 2dd6529c69e338d923164859f1d0e14db726c17c..88582bd39b0666a1cdd77e9e3ef8c82c384d5ab0 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.869789                       # Nu
 sim_ticks                                2869788970000                       # Number of ticks simulated
 final_tick                               2869788970000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 480288                       # Simulator instruction rate (inst/s)
-host_op_rate                                   580935                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10477281069                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 611892                       # Number of bytes of host memory used
-host_seconds                                   273.91                       # Real time elapsed on the host
+host_inst_rate                                1069345                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1293434                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23327334867                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 660408                       # Number of bytes of host memory used
+host_seconds                                   123.02                       # Real time elapsed on the host
 sim_insts                                   131553574                       # Number of instructions simulated
 sim_ops                                     159121622                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -541,7 +541,7 @@ system.cpu0.num_func_calls                   12675179                       # nu
 system.cpu0.num_conditional_control_insts     15700187                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                   123360698                       # number of integer instructions
 system.cpu0.num_fp_insts                         9756                       # number of float instructions
-system.cpu0.num_int_register_reads          227087077                       # number of times the integer registers were read
+system.cpu0.num_int_register_reads          227063318                       # number of times the integer registers were read
 system.cpu0.num_int_register_writes          85717152                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                7496                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
@@ -1462,7 +1462,7 @@ system.cpu1.num_func_calls                    1029080                       # nu
 system.cpu1.num_conditional_control_insts      1813608                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    17804295                       # number of integer instructions
 system.cpu1.num_fp_insts                         1857                       # number of float instructions
-system.cpu1.num_int_register_reads           32314180                       # number of times the integer registers were read
+system.cpu1.num_int_register_reads           32308777                       # number of times the integer registers were read
 system.cpu1.num_int_register_writes          12487661                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1341                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
index 03b467a01052604e80ba5738dc5b732df73d2894..263610058d49c7f7e0064f26715703ebfe62d388 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
@@ -158,8 +158,8 @@ ata1.00: 1048320 sectors, multi 0: LBA
 ata1.00: configured for UDMA/33\r
 scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5\r
 sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
 sd 0:0:0:0: [sda] Write Protect is off\r
+sd 0:0:0:0: Attached scsi generic sg0 type 0\r
 sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
 sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
  sda: sda1\r

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 56d82517df04b4bdfcfce37940adbf8ac8fb4ddd..26772351407ddc7d20110615c4dae489b74a05df 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -890,6 +890,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 244ffaad42d9b10cfe0cbb9aa5006ca0f6380382..b2ef0166630fa60875ce10c13eef282206a4f7f7 100755 (executable)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2909596171500 because m5_exit instruction encountered
+Exiting @ tick 2909586837500 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index e1254a2d4ba77327f0e2a1a57f6e9dc588d33d04..b784b788d61b7c68f5aecb0a44577d6ce1051a12 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.909587                       # Nu
 sim_ticks                                2909586837500                       # Number of ticks simulated
 final_tick                               2909586837500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 495886                       # Simulator instruction rate (inst/s)
-host_op_rate                                   597884                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            12830006266                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 573732                       # Number of bytes of host memory used
-host_seconds                                   226.78                       # Real time elapsed on the host
+host_inst_rate                                1061137                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1279400                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            27454664075                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 618904                       # Number of bytes of host memory used
+host_seconds                                   105.98                       # Real time elapsed on the host
 sim_insts                                   112457035                       # Number of instructions simulated
 sim_ops                                     135588119                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -499,7 +499,7 @@ system.cpu.num_func_calls                     9892146                       # nu
 system.cpu.num_conditional_control_insts     15230571                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    119893391                       # number of integer instructions
 system.cpu.num_fp_insts                         11161                       # number of float instructions
-system.cpu.num_int_register_reads           218063466                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           218036740                       # number of times the integer registers were read
 system.cpu.num_int_register_writes           82646452                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index 76353e776bc72c658c1d90427108bad766812927..146e2473753572249589b41eb267fefb605d8230 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -591,14 +591,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -625,6 +625,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
@@ -958,6 +965,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
index e0323518d0adba614b901301001f7c6219da3bff..cf30e237d82d53fe82194e4213d8693aa2563ca1 100755 (executable)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
@@ -42,7 +42,3 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
index 5247994405c5cffb4742a945d97eb0539831703b..9158d24040a22a94eefc29e842bd4e3bf16bf85d 100755 (executable)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index cde05e946004d28d9bc84670560781e4859b8b35..db738381c5f79e5e5b77d97947466afa8255d0e6 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783854                       # Nu
 sim_ticks                                2783853866500                       # Number of ticks simulated
 final_tick                               2783853866500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 760140                       # Simulator instruction rate (inst/s)
-host_op_rate                                   925348                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14821821018                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 577060                       # Number of bytes of host memory used
-host_seconds                                   187.82                       # Real time elapsed on the host
+host_inst_rate                                1657563                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2017817                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            32320507686                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 622988                       # Number of bytes of host memory used
+host_seconds                                    86.13                       # Real time elapsed on the host
 sim_insts                                   142770436                       # Number of instructions simulated
 sim_ops                                     173800089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -236,7 +236,7 @@ system.cpu0.num_func_calls                    8694385                       # nu
 system.cpu0.num_conditional_control_insts      9459738                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                    77491639                       # number of integer instructions
 system.cpu0.num_fp_insts                         5273                       # number of float instructions
-system.cpu0.num_int_register_reads          144069521                       # number of times the integer registers were read
+system.cpu0.num_int_register_reads          144056693                       # number of times the integer registers were read
 system.cpu0.num_int_register_writes          54447639                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                4051                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1224                       # number of times the floating registers were written
@@ -605,7 +605,7 @@ system.cpu1.num_func_calls                    8179291                       # nu
 system.cpu1.num_conditional_control_insts      9270395                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    75668279                       # number of integer instructions
 system.cpu1.num_fp_insts                         6211                       # number of float instructions
-system.cpu1.num_int_register_reads          140985352                       # number of times the integer registers were read
+system.cpu1.num_int_register_reads          140970750                       # number of times the integer registers were read
 system.cpu1.num_int_register_writes          52729833                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                4721                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes               1492                       # number of times the floating registers were written

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
index fd51e60961f118d4cef117cdab609f6a07130624..c0c7c3972bb136c08ce2686079bf6cdd73e872ec 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -583,14 +583,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -617,6 +617,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -1014,6 +1021,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
index 40c7f8e08d4a2e752b8563a7a0e8d919eb671863..dfb86f06cfd0dde6ac988d5e798dced4d09e0bc4 100755 (executable)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index 444bbfba5278dd5a5e6bb11dda696136e707543d..9730cf287768370b4cf40f44b3bdbd52c3f3b053 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.903880                       # Nu
 sim_ticks                                2903879904500                       # Number of ticks simulated
 final_tick                               2903879904500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 505304                       # Simulator instruction rate (inst/s)
-host_op_rate                                   609246                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            13046252349                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 577060                       # Number of bytes of host memory used
-host_seconds                                   222.58                       # Real time elapsed on the host
+host_inst_rate                                1077958                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1299696                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            27831365956                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 624164                       # Number of bytes of host memory used
+host_seconds                                   104.34                       # Real time elapsed on the host
 sim_insts                                   112472358                       # Number of instructions simulated
 sim_ops                                     135608167                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -533,7 +533,7 @@ system.cpu0.num_func_calls                    4936884                       # nu
 system.cpu0.num_conditional_control_insts      7560751                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                    59477787                       # number of integer instructions
 system.cpu0.num_fp_insts                         5777                       # number of float instructions
-system.cpu0.num_int_register_reads          108128339                       # number of times the integer registers were read
+system.cpu0.num_int_register_reads          108114498                       # number of times the integer registers were read
 system.cpu0.num_int_register_writes          41101378                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                4484                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1294                       # number of times the floating registers were written
@@ -1146,7 +1146,7 @@ system.cpu1.num_func_calls                    4958421                       # nu
 system.cpu1.num_conditional_control_insts      7671718                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    60434186                       # number of integer instructions
 system.cpu1.num_fp_insts                         5384                       # number of float instructions
-system.cpu1.num_int_register_reads          109968090                       # number of times the integer registers were read
+system.cpu1.num_int_register_reads          109955204                       # number of times the integer registers were read
 system.cpu1.num_int_register_writes          41558584                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                3965                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes               1422                       # number of times the floating registers were written

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index 3c670644048fc42bf648605db0368595ac4c6211..97296d3da6ed9cb22e06dab2c05c0a6db7d25c81 100755 (executable)
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
@@ -9,4 +11,4 @@ command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/li
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 17170000 because target called exit()
+Exiting @ tick 17232500 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 203ef51d3985093a904998df5196877258060a60..9149a2fa0dfeca23e54d716f9d726323d9de2dac 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    17232500                       # Number of ticks simulated
 final_tick                                   17232500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37479                       # Simulator instruction rate (inst/s)
-host_op_rate                                    43886                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              140595410                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265936                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                  74741                       # Simulator instruction rate (inst/s)
+host_op_rate                                    87520                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              280399381                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309668                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -554,7 +554,7 @@ system.cpu.rename.IQFullEvents                    166                       # Nu
 system.cpu.rename.LQFullEvents                    130                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                   1074                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands               11638                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 52722                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups                 52321                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups            12347                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               199                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
@@ -571,7 +571,7 @@ system.cpu.iq.iqNonSpecInstsAdded                  43                       # Nu
 system.cpu.iq.iqInstsIssued                      8103                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                38                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedInstsExamined            4832                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        12413                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined        12329                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              6                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples         13213                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         0.613260                       # Number of insts issued each cycle
@@ -791,7 +791,7 @@ system.cpu.int_regfile_writes                    4270                       # nu
 system.cpu.fp_regfile_reads                        32                       # number of floating regfile reads
 system.cpu.cc_regfile_reads                     27801                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                     3276                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    3010                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    2978                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
 system.cpu.dcache.tags.tagsinuse            88.359063                       # Cycle average of tags in use

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index 5c8d62c82e65257f48a27a8da2e78e27e850253b..e4ae040246fbab669fc5188e755f8e562f1c2976 100755 (executable)
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
@@ -9,4 +11,4 @@ command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/li
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 18741000 because target called exit()
+Exiting @ tick 18821000 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 17fbc7c06681d788c8729aa0205df2b17676c4d5..d093f5febd95d8e64e9d92019b0c979d45a17f26 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000019                       # Nu
 sim_ticks                                    18821000                       # Number of ticks simulated
 final_tick                                   18821000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  22479                       # Simulator instruction rate (inst/s)
-host_op_rate                                    26323                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               92110547                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261716                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  77535                       # Simulator instruction rate (inst/s)
+host_op_rate                                    90790                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              317684946                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305172                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -435,7 +435,7 @@ system.cpu.rename.IQFullEvents                      1                       # Nu
 system.cpu.rename.LQFullEvents                     28                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                    744                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands                9450                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 41158                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups                 41121                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups             9999                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                17                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5494                       # Number of HB maps that are committed
@@ -672,7 +672,7 @@ system.cpu.int_regfile_writes                    3787                       # nu
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.cc_regfile_reads                     24229                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                     2921                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                    2578                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    2562                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements                 1                       # number of replacements
 system.cpu.dcache.tags.tagsinuse            84.368926                       # Cycle average of tags in use

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index bcfa4927020bb9351d982612f73c6266d76312d3..12cffc971fe3ffbb6938a263a1c4ed921b13c97f 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2695000                       # Number of ticks simulated
 final_tick                                    2695000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 274500                       # Simulator instruction rate (inst/s)
-host_op_rate                                   321069                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              160714630                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254660                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 555825                       # Simulator instruction rate (inst/s)
+host_op_rate                                   650110                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              325439975                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298640                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -283,7 +283,7 @@ system.cpu.num_func_calls                         203                       # nu
 system.cpu.num_conditional_control_insts          722                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         4624                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads                7607                       # number of times the integer registers were read
+system.cpu.num_int_register_reads                7572                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               2728                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
index 994e2e64600a64e6564637cbde3911b6d8ecd767..98eb95060260f7b8167e01cd2026b9f7a0b143b7 100755 (executable)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 6f1efaf21c85e43d8c555e05cfa2cfaa454488a1..80bb8332d81f7cb433403e4250902695b1fe37de 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2695000                       # Number of ticks simulated
 final_tick                                    2695000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 363981                       # Simulator instruction rate (inst/s)
-host_op_rate                                   425522                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              212904964                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254404                       # Number of bytes of host memory used
+host_inst_rate                                 589705                       # Simulator instruction rate (inst/s)
+host_op_rate                                   689852                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              345334530                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297616                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
@@ -164,7 +164,7 @@ system.cpu.num_func_calls                         203                       # nu
 system.cpu.num_conditional_control_insts          722                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         4624                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads                7607                       # number of times the integer registers were read
+system.cpu.num_int_register_reads                7572                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               2728                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index 1bcd9c70221d606ff5daefe0afcf2c4ffb583401..daa7694077ffe9d67f05c8b4937361bd942231ad 100755 (executable)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index e99784abb010ecdef45169541eca32bb4f36a02f..78aca14dcef5a43f7e9fc65ba0391ae63c51a361 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28298500                       # Number of ticks simulated
 final_tick                                   28298500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 343617                       # Simulator instruction rate (inst/s)
-host_op_rate                                   400476                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2123290642                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 263372                       # Number of bytes of host memory used
+host_inst_rate                                 311400                       # Simulator instruction rate (inst/s)
+host_op_rate                                   363255                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1927478424                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306584                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4566                       # Number of instructions simulated
 sim_ops                                          5330                       # Number of ops (including micro ops) simulated
@@ -158,7 +158,7 @@ system.cpu.num_func_calls                         203                       # nu
 system.cpu.num_conditional_control_insts          722                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         4624                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads                7573                       # number of times the integer registers were read
+system.cpu.num_int_register_reads                7538                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               2728                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written

diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
index e03d9d874c80fa95435ce7f75f4c414512b20f34..48bc9cc41ecf48a9f67b87597d8b7633ea662fa9 100755 (executable)
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 

diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
index 6a638c32666c60013e383f7ddd0aae244af26fba..0fe3c4c97d93b0f2681dd71f66139600b3381f8e 100644 (file)
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000326                       # Nu
 sim_ticks                                   325849000                       # Number of ticks simulated
 final_tick                                  325849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 156546                       # Simulator instruction rate (inst/s)
-host_op_rate                                   180975                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10214317316                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 647364                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 204518                       # Simulator instruction rate (inst/s)
+host_op_rate                                   236491                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            13350749795                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 689808                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -397,7 +397,7 @@ system.cpu.num_func_calls                         215                       # nu
 system.cpu.num_conditional_control_insts          800                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         4977                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads                8084                       # number of times the integer registers were read
+system.cpu.num_int_register_reads                8049                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               2992                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written

diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
index ba1e402113df87a09e33dc8c7c94153fe37edcb5..27e9cb7938c2331bb6abd14fe1cc0c8a6a91b079 100755 (executable)
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 

diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
index 1fca855befebbed992b10919105a221c2b39d9fd..825faee95a72a356fdaee5eafc7f3f51494244d8 100644 (file)
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000050                       # Nu
 sim_ticks                                    49855000                       # Number of ticks simulated
 final_tick                                   49855000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 388067                       # Simulator instruction rate (inst/s)
-host_op_rate                                   448196                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3866626926                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 651460                       # Number of bytes of host memory used
+host_inst_rate                                 372227                       # Simulator instruction rate (inst/s)
+host_op_rate                                   430264                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3715181399                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 693900                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
@@ -377,7 +377,7 @@ system.cpu.num_func_calls                         215                       # nu
 system.cpu.num_conditional_control_insts          800                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         4977                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads                8084                       # number of times the integer registers were read
+system.cpu.num_int_register_reads                8049                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               2992                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written

diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
index 3e4fd6df8c5b88e497f2f07d4d16bf387236bbf9..0868020ea72a31fe449e69fbc8593acf0233edf4 100755 (executable)
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 

diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index edbbb089b37bcb454049f989a0fee678f68b5e59..05fda579807e3384208a16ca34d401c5d067ca91 100644 (file)
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.054141                       # Nu
 sim_ticks                                 54141000500                       # Number of ticks simulated
 final_tick                                54141000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 991860                       # Simulator instruction rate (inst/s)
-host_op_rate                                   996799                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              592702245                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 389728                       # Number of bytes of host memory used
-host_seconds                                    91.35                       # Real time elapsed on the host
+host_inst_rate                                2133242                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2143866                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1274754382                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 434732                       # Number of bytes of host memory used
+host_seconds                                    42.47                       # Real time elapsed on the host
 sim_insts                                    90602408                       # Number of instructions simulated
 sim_ops                                      91053639                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -164,7 +164,7 @@ system.cpu.num_func_calls                      112245                       # nu
 system.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                     72326352                       # number of integer instructions
 system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           124257699                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           124257600                       # number of times the integer registers were read
 system.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written

diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
index cd6f7e703c663b20aa3c56865a6effcac448d7c4..6c1776dde5acb5fb2f66f8d6b7f30fea5ac4b205 100755 (executable)
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 

diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 60ec365147cea435e3cd92f7934b328863143239..1f4d8614e644aa24938b5b9b6e9f8c84a4d7b693 100644 (file)
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.147149                       # Nu
 sim_ticks                                147148719500                       # Number of ticks simulated
 final_tick                               147148719500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 596574                       # Simulator instruction rate (inst/s)
-host_op_rate                                   599539                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              969178238                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 398700                       # Number of bytes of host memory used
-host_seconds                                   151.83                       # Real time elapsed on the host
+host_inst_rate                                1356153                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1362892                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2203169070                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 444740                       # Number of bytes of host memory used
+host_seconds                                    66.79                       # Real time elapsed on the host
 sim_insts                                    90576862                       # Number of instructions simulated
 sim_ops                                      91026991                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -158,7 +158,7 @@ system.cpu.num_func_calls                      112245                       # nu
 system.cpu.num_conditional_control_insts     15520157                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                     72326352                       # number of integer instructions
 system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           124237033                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           124236934                       # number of times the integer registers were read
 system.cpu.num_int_register_writes           52782988                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written

diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 9dc871248095b201453f97085641469d436baf14..545d841c616bb5750f7454dbcc1a2382e243f70c 100644 (file)
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.048960                       # Nu
 sim_ticks                                 48960022500                       # Number of ticks simulated
 final_tick                                48960022500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 866033                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1107536                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              597928109                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264428                       # Number of bytes of host memory used
-host_seconds                                    81.88                       # Real time elapsed on the host
+host_inst_rate                                1798045                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2299450                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1241408996                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309432                       # Number of bytes of host memory used
+host_seconds                                    39.44                       # Real time elapsed on the host
 sim_insts                                    70913204                       # Number of instructions simulated
 sim_ops                                      90688159                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -164,7 +164,7 @@ system.cpu.num_func_calls                     3311620                       # nu
 system.cpu.num_conditional_control_insts      9253630                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                     81528528                       # number of integer instructions
 system.cpu.num_fp_insts                            56                       # number of float instructions
-system.cpu.num_int_register_reads           141479386                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           141479271                       # number of times the integer registers were read
 system.cpu.num_int_register_writes           53916335                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written

diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index b5cf25ee6f1aad7c7b0a4689bda9a4464b8b4149..f303216c1ba6376dc0410e21c67d7a35de670f2b 100644 (file)
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.128077                       # Nu
 sim_ticks                                128076834500                       # Number of ticks simulated
 final_tick                               128076834500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 531513                       # Simulator instruction rate (inst/s)
-host_op_rate                                   678593                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              967329196                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273400                       # Number of bytes of host memory used
-host_seconds                                   132.40                       # Real time elapsed on the host
+host_inst_rate                                1113892                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1422128                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2027232976                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319564                       # Number of bytes of host memory used
+host_seconds                                    63.18                       # Real time elapsed on the host
 sim_insts                                    70373651                       # Number of instructions simulated
 sim_ops                                      89847385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -165,7 +165,7 @@ system.cpu.num_func_calls                     3311620                       # nu
 system.cpu.num_conditional_control_insts      9253630                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                     81528528                       # number of integer instructions
 system.cpu.num_fp_insts                            56                       # number of float instructions
-system.cpu.num_int_register_reads           141328550                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           141328435                       # number of times the integer registers were read
 system.cpu.num_int_register_writes           53916335                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written

diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout
index a3aed918d8b4f96a42435caaa6a6a98c8b21fff9..01f7a2d96c62b0bc792a4951230f7e4694e3d107 100755 (executable)
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
@@ -6,8 +8,6 @@ gem5 started Jan 21 2016 14:46:39
 gem5 executing on zizzer, pid 20766
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic
 
-Couldn't unlink  build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink  build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 

diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 99598cd5b0963e1d51b0658d91f03e7e907d2dd7..5f1cdd65ce78bfce46523614768b52bcde205eb7 100644 (file)
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.099596                       # Nu
 sim_ticks                                 99596491500                       # Number of ticks simulated
 final_tick                                99596491500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1040518                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1096874                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              601401466                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259948                       # Number of bytes of host memory used
-host_seconds                                   165.61                       # Real time elapsed on the host
+host_inst_rate                                2176341                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2294214                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1257887009                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304976                       # Number of bytes of host memory used
+host_seconds                                    79.18                       # Real time elapsed on the host
 sim_insts                                   172317410                       # Number of instructions simulated
 sim_ops                                     181650342                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -164,7 +164,7 @@ system.cpu.num_func_calls                     3545028                       # nu
 system.cpu.num_conditional_control_insts     32201008                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    143085668                       # number of integer instructions
 system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_int_register_reads           241970171                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           238310719                       # number of times the integer registers were read
 system.cpu.num_int_register_writes           98192342                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written

diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout
index 0a9d1a43d4dbce6fa8993c1820853361e2e2b72e..64f9b8146d36994a36936d812010d029891b8182 100755 (executable)
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
@@ -6,8 +8,6 @@ gem5 started Jan 21 2016 14:46:22
 gem5 executing on zizzer, pid 20735
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing
 
-Couldn't unlink  build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink  build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 

diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index da877a9a0b0a2795ea34197f252b0f44781cb7d2..84721fe7c622903bad2809b5afe44ada9b4d8eb9 100644 (file)
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.230198                       # Nu
 sim_ticks                                230197694500                       # Number of ticks simulated
 final_tick                               230197694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 718293                       # Simulator instruction rate (inst/s)
-host_op_rate                                   757262                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              962214385                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 268920                       # Number of bytes of host memory used
-host_seconds                                   239.24                       # Real time elapsed on the host
+host_inst_rate                                1495549                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1576687                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2003415873                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314964                       # Number of bytes of host memory used
+host_seconds                                   114.90                       # Real time elapsed on the host
 sim_insts                                   171842484                       # Number of instructions simulated
 sim_ops                                     181165371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -158,7 +158,7 @@ system.cpu.num_func_calls                     3545028                       # nu
 system.cpu.num_conditional_control_insts     32201008                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    143085668                       # number of integer instructions
 system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_int_register_reads           242291225                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           238631773                       # number of times the integer registers were read
 system.cpu.num_int_register_writes           98192342                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written