Update .gitmodules
authoratommann <atommann@gmail.com>
Mon, 12 Aug 2019 14:20:34 +0000 (22:20 +0800)
committerGitHub <noreply@github.com>
Mon, 12 Aug 2019 14:20:34 +0000 (22:20 +0800)
http to https

.gitmodules

index dbaa50b4fa885c2f14ce2e579a594d4f09550cd5..17eaf734d30bb58526a0fc3ce4c43102c1ae8c4f 100644 (file)
@@ -18,7 +18,7 @@
        url = https://github.com/enjoy-digital/VexRiscv-verilog.git
 [submodule "litex/soc/cores/cpu/minerva/verilog"]
        path = litex/soc/cores/cpu/minerva/verilog
-       url = http://github.com/enjoy-digital/minerva-verilog
+       url = https://github.com/enjoy-digital/minerva-verilog
 [submodule "litex/soc/cores/cpu/rocket/verilog"]
        path = litex/soc/cores/cpu/rocket/verilog
        url = https://github.com/enjoy-digital/rocket-litex-verilog