Remove SRL16/32 from cells_xtra

diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 0480410f5d5d8df260f3af6e89a0f5b629e17a5f..8cc90d1f2b57d2ce1579fc3c132a7b1e1d6da83e 100644 (file)
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -134,8 +134,8 @@ function xtract_cell_decl()
        xtract_cell_decl ROM256X1
        xtract_cell_decl ROM32X1
        xtract_cell_decl ROM64X1
-       xtract_cell_decl SRL16E
-       xtract_cell_decl SRLC32E
+       #xtract_cell_decl SRL16E
+       #xtract_cell_decl SRLC32E
        xtract_cell_decl STARTUPE2
        xtract_cell_decl USR_ACCESSE2
        xtract_cell_decl XADC

diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 8d8b91ddcd0c2a1f69ddaf85664630e3132a20a9..21db6a6bdebee6b87e0aecbe93a15fd8325911f0 100644 (file)
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -3824,22 +3824,6 @@ module ROM64X1 (...);
     input A0, A1, A2, A3, A4, A5;
 endmodule
 
-module SRL16E (...);
-    parameter [15:0] INIT = 16'h0000;
-    parameter [0:0] IS_CLK_INVERTED = 1'b0;
-    output Q;
-    input A0, A1, A2, A3, CE, CLK, D;
-endmodule
-
-module SRLC32E (...);
-    parameter [31:0] INIT = 32'h00000000;
-    parameter [0:0] IS_CLK_INVERTED = 1'b0;
-    output Q;
-    output Q31;
-    input [4:0] A;
-    input CE, CLK, D;
-endmodule
-
 module STARTUPE2 (...);
     parameter PROG_USR = "FALSE";
     parameter real SIM_CCLK_FREQ = 0.0;