projects
/
riscv-isa-sim.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(from:
1da69b9
)
Implement Hauser misa.C misalignment proposal (#187)
author
Andrew Waterman
<aswaterman@gmail.com>
Thu, 22 Mar 2018 00:19:16 +0000
(17:19 -0700)
committer
GitHub
<noreply@github.com>
Thu, 22 Mar 2018 00:19:16 +0000
(17:19 -0700)
See https://github.com/riscv/riscv-isa-manual/commit/
0472bcdd166f45712492829a250e228bb45fa5e7
- Reads of xEPC[1] are masked when RVC is disabled
- Writes to MISA are suppressed if they would cause a misaligned fetch
- Misaligned PCs no longer need to be checked upon fetch
No differences found