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tests: add ecp5 latch testcase with -abc9
author
Eddie Hung
<eddie@fpgeh.com>
Mon, 25 May 2020 23:39:16 +0000
(16:39 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Mon, 25 May 2020 23:39:16 +0000
(16:39 -0700)
tests/arch/ecp5/latches_abc9.ys
[new file with mode: 0644]
patch
|
blob
diff --git a/tests/arch/ecp5/latches_abc9.ys
b/tests/arch/ecp5/latches_abc9.ys
new file mode 100644
(file)
index 0000000..
ca31822
--- /dev/null
+++ b/
tests/arch/ecp5/latches_abc9.ys
@@ -0,0
+1,16
@@
+read_verilog <<EOT
+module top(input e, d, output q);
+reg l;
+always @*
+ if (e)
+ l = ~d;
+assign q = ~l;
+endmodule
+EOT
+proc
+design -save gold
+
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ecp5 -abc9
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT4 %% t:* %D