+2012-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/arm/arm.h (TARGET_FPU_ARMV8): New macro.
+ * config/arm/arm.md (UNSPEC_VRINTZ, UNSPEC_VRINTP, UNSPEC_VRINTM)
+ (UNSPEC_VRINTR, UNSPEC_VRINTX, UNSPEC_VRINTA): New unspecs.
+ (f_rints, f_rintd): New types.
+ * config/arm/iterators.md (VRINT): New int iterator.
+ (F_fma_type): Remove.
+ (vfp_type): New mode attribute.
+ (vfp_double_cond): Likewise.
+ (vrint_pattern, vrint_variant, vrint_predicable): New int attribute.
+ * config/arm/vfp.md (fma<SDF:mode>4): Use vfp_type iterator
+ instead of F_fma_type.
+ (*fmsub<SDF:mode>4, *fnmsub<SDF:mode>4, *fnmadd<SDF:mode>4): Likewise.
+ (<vrint_pattern><SDF:mode>2): New pattern.
+
2012-11-26 Eric Botcazou <ebotcazou@adacore.com>
* fold-const.c (const_binop): Adjust comment.
/* FPU supports fused-multiply-add operations. */
#define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
+/* FPU is ARMv8 compatible. */
+#define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8)
+
/* FPU supports Crypto extensions. */
#define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
UNSPEC_UNALIGNED_STORE ; Same for str/strh.
UNSPEC_PIC_UNIFIED ; Create a common pic addressing form.
UNSPEC_LL ; Represent an unpaired load-register-exclusive.
+ UNSPEC_VRINTZ ; Represent a float to integral float rounding
+ ; towards zero.
+ UNSPEC_VRINTP ; Represent a float to integral float rounding
+ ; towards +Inf.
+ UNSPEC_VRINTM ; Represent a float to integral float rounding
+ ; towards -Inf.
+ UNSPEC_VRINTR ; Represent a float to integral float rounding
+ ; FPSCR rounding mode.
+ UNSPEC_VRINTX ; Represent a float to integral float rounding
+ ; FPSCR rounding mode and signal inexactness.
+ UNSPEC_VRINTA ; Represent a float to integral float rounding
+ ; towards nearest, ties away from zero.
])
;; UNSPEC_VOLATILE Usage:
fmuld,\
fmacs,\
fmacd,\
+ f_rints,\
+ f_rintd,\
f_flag,\
f_loads,\
f_loadd,\
;; Right shifts
(define_code_iterator rshifts [ashiftrt lshiftrt])
+;;----------------------------------------------------------------------------
+;; Int iterators
+;;----------------------------------------------------------------------------
+
+(define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
+ UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
+
;;----------------------------------------------------------------------------
;; Mode attributes
;;----------------------------------------------------------------------------
;; Mode attribute for vshll.
(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
-;; Mode attributes used for fused-multiply-accumulate VFP support
+;; Mode attributes used for VFP support.
(define_mode_attr F_constraint [(SF "t") (DF "w")])
-(define_mode_attr F_fma_type [(SF "fmacs") (DF "fmacd")])
+(define_mode_attr vfp_type [(SF "s") (DF "d")])
+(define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")])
;;----------------------------------------------------------------------------
;; Code attributes
(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
+;;----------------------------------------------------------------------------
+;; Int attributes
+;;----------------------------------------------------------------------------
+
+;; Standard names for floating point to integral rounding instructions.
+(define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil")
+ (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor")
+ (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")])
+
+;; Suffixes for vrint instructions specifying rounding modes.
+(define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p")
+ (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
+ (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
+
+;; Some of the vrint instuctions are predicable.
+(define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no")
+ (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
+ (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "type" "<F_fma_type>")]
+ (set_attr "type" "fmac<vfp_type>")]
)
(define_insn "*fmsub<SDF:mode>4"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "type" "<F_fma_type>")]
+ (set_attr "type" "fmac<vfp_type>")]
)
(define_insn "*fnmsub<SDF:mode>4"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "type" "<F_fma_type>")]
+ (set_attr "type" "fmac<vfp_type>")]
)
(define_insn "*fnmadd<SDF:mode>4"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "type" "<F_fma_type>")]
+ (set_attr "type" "fmac<vfp_type>")]
)
[(set_attr "type" "f_stored")]
)
+;; VRINT round to integral instructions.
+;; Invoked for the patterns: btruncsf2, btruncdf2, ceilsf2, ceildf2,
+;; roundsf2, rounddf2, floorsf2, floordf2, nearbyintsf2, nearbyintdf2,
+;; rintsf2, rintdf2.
+(define_insn "<vrint_pattern><SDF:mode>2"
+ [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ (unspec:SDF [(match_operand:SDF 1
+ "register_operand" "<F_constraint>")]
+ VRINT))]
+ "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+ "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
+ [(set_attr "predicable" "<vrint_predicable>")
+ (set_attr "type" "f_rint<vfp_type>")]
+)
;; Unimplemented insns:
;; fldm*
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