add ls180.mdwn auto-generated

diff --git a/180nm_Oct2020.mdwn b/180nm_Oct2020.mdwn
index 92ee82e40df8797274a5f8cee61f817521f424f1..00867e33df152ea5471400e4dc50870ee60feda2 100644 (file)
--- a/180nm_Oct2020.mdwn
+++ b/180nm_Oct2020.mdwn
@@ -28,6 +28,7 @@ Links:
 * [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
   GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
   and that actually might even be it.
+* [[180nm_Oct2020/ls180]] actual auto-generated pinouts by pinmux program
 
 ## Secondary priorities
 

diff --git a/180nm_Oct2020/interfaces.mdwn b/180nm_Oct2020/interfaces.mdwn
index 5bf6d96af27300378febc168cebf8c2be05e9f63..d08ff53fdbfb829f0efa7b9ba9df65d3bc58dade 100644 (file)
--- a/180nm_Oct2020/interfaces.mdwn
+++ b/180nm_Oct2020/interfaces.mdwn
@@ -1,5 +1,7 @@
 # Interfaces for the 180nm Oct2020 ASIC
 
+[[ls180]] actual interfaces
+
 [List Link](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006355.html)
 
 Bugreport and discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=304>

diff --git a/180nm_Oct2020/ls180.mdwn b/180nm_Oct2020/ls180.mdwn
new file mode 100644 (file)
index 0000000..86041c2
--- /dev/null
+++ b/180nm_Oct2020/ls180.mdwn
@@ -0,0 +1,267 @@
+# Pinouts (PinMux)
+auto-generated by [[pinouts.py]]
+
+[[!toc  ]]
+
+
+## Bank N (32 pins, width 2)
+
+| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
+| --- | ----------- | ----------- | ----------- | ----------- |
+|   0 | N VSS_0     |             |
+|   1 | N VDD_0     |             |
+|   2 | N SDR_DQM0  |             |
+|   3 | N SDR_D0    |             |
+|   4 | N SDR_D1    |             |
+|   5 | N SDR_D2    |             |
+|   6 | N SDR_D3    |             |
+|   7 | N SDR_D4    |             |
+|   8 | N SDR_D5    |             |
+|   9 | N SDR_D6    |             |
+|  10 | N SDR_D7    |             |
+|  11 | N SDR_AD0   |             |
+|  12 | N SDR_AD1   |             |
+|  13 | N SDR_AD2   |             |
+|  14 | N SDR_AD3   |             |
+|  15 | N SDR_AD4   |             |
+|  16 | N SDR_AD5   |             |
+|  17 | N SDR_AD6   |             |
+|  18 | N SDR_AD7   |             |
+|  19 | N SDR_AD8   |             |
+|  20 | N SDR_AD9   |             |
+|  21 | N SDR_BA0   |             |
+|  22 | N SDR_BA1   |             |
+|  23 | N SDR_CLK   |             |
+|  24 | N SDR_CKE   |             |
+|  25 | N SDR_RASn  |             |
+|  26 | N SDR_CASn  |             |
+|  27 | N SDR_WEn   |             |
+|  28 | N SDR_CSn0  |             |
+|  30 | N VSS_0     |             |
+|  31 | N VDD_0     |             |
+
+## Bank E (32 pins, width 2)
+
+| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
+| --- | ----------- | ----------- | ----------- | ----------- |
+|  32 | E VSS_1     |             |
+|  33 | E SDR_SDRAD10 |             |
+|  34 | E SDR_SDRAD11 |             |
+|  35 | E SDR_SDRAD12 |             |
+|  36 | E SDR_DQM1  |             |
+|  37 | E SDR_D8    |             |
+|  38 | E SDR_D9    |             |
+|  39 | E SDR_D10   |             |
+|  40 | E SDR_D11   |             |
+|  41 | E SDR_D12   |             |
+|  42 | E SDR_D13   |             |
+|  43 | E SDR_D14   |             |
+|  44 | E SDR_D15   |             |
+|  45 | E VDD_1     |             |
+|  46 | E GPIOE_E8  |             |
+|  47 | E GPIOE_E9  |             |
+|  48 | E GPIOE_E10 |             |
+|  49 | E GPIOE_E11 |             |
+|  50 | E GPIOE_E12 |             |
+|  51 | E GPIOE_E13 |             |
+|  52 | E GPIOE_E14 |             |
+|  53 | E GPIOE_E15 |             |
+|  55 | E VSS_1     |             |
+|  56 | E JTAG_TMS  |             |
+|  57 | E JTAG_TDI  |             |
+|  58 | E JTAG_TDO  |             |
+|  59 | E JTAG_TCK  |             |
+|  63 | E VDD_1     |             |
+
+## Bank S (32 pins, width 2)
+
+| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
+| --- | ----------- | ----------- | ----------- | ----------- |
+|  64 | S VSS_1     |             |
+|  65 | S CLK_0     |             |
+|  66 | S RST_0     |             |
+|  67 | S MSPI0_CK  |             |
+|  68 | S MSPI0_NSS |             |
+|  69 | S MSPI0_MOSI |             |
+|  70 | S MSPI0_MISO |             |
+|  71 | S UART0_TX  |             |
+|  72 | S UART0_RX  |             |
+|  95 | S VDD_1     |             |
+
+## Bank W (32 pins, width 2)
+
+| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
+| --- | ----------- | ----------- | ----------- | ----------- |
+|  96 | W VSS_1     |             |
+|  97 | W PWM_0     |             |
+|  98 | W PWM_1     |             |
+|  99 | W EINT_0    |             |
+| 100 | W EINT_1    |             |
+| 101 | W EINT_2    |             |
+| 102 | W MSPI1_CK  |             |
+| 103 | W MSPI1_NSS |             |
+| 104 | W MSPI1_MOSI |             |
+| 105 | W MSPI1_MISO |             |
+| 106 | W MMC0_CMD  |             |
+| 107 | W MMC0_CLK  |             |
+| 108 | W MMC0_D0   |             |
+| 109 | W MMC0_D1   |             |
+| 110 | W MMC0_D2   |             |
+| 111 | W MMC0_D3   |             |
+| 127 | W VDD_1     |             |
+
+# Pinouts (Fixed function)
+
+# Functions (PinMux)
+
+auto-generated by [[pinouts.py]]
+
+
+# Pinmap for Libre-SOC 180nm
+
+## ULPI0/8
+
+user-facing: internal (on Card), USB-OTG ULPI PHY
+
+
+## ULPI1
+
+dual USB2 Host ULPI PHY
+
+
+## MMC1
+
+
+## MMC2
+
+
+## SD0
+
+user-facing: internal (on Card), multiplexed with JTAG
+and UART2, for debug purposes
+
+
+## UART0
+
+
+
+
+## TWI0
+
+
+## MSPI0
+
+
+## B3:SD1
+
+
+## Unused Pinouts (spare as GPIO) for 'Libre-SOC 180nm'
+
+| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
+| --- | ----------- | ----------- | ----------- | ----------- |
+|   0 | N VSS_0     |             |             |             |
+|   1 | N VDD_0     |             |             |             |
+|   2 | N SDR_DQM0  |             |             |             |
+|   3 | N SDR_D0    |             |             |             |
+|   4 | N SDR_D1    |             |             |             |
+|   5 | N SDR_D2    |             |             |             |
+|   6 | N SDR_D3    |             |             |             |
+|   7 | N SDR_D4    |             |             |             |
+|   8 | N SDR_D5    |             |             |             |
+|   9 | N SDR_D6    |             |             |             |
+|  10 | N SDR_D7    |             |             |             |
+|  11 | N SDR_AD0   |             |             |             |
+|  12 | N SDR_AD1   |             |             |             |
+|  13 | N SDR_AD2   |             |             |             |
+|  14 | N SDR_AD3   |             |             |             |
+|  15 | N SDR_AD4   |             |             |             |
+|  16 | N SDR_AD5   |             |             |             |
+|  17 | N SDR_AD6   |             |             |             |
+|  18 | N SDR_AD7   |             |             |             |
+|  19 | N SDR_AD8   |             |             |             |
+|  20 | N SDR_AD9   |             |             |             |
+|  21 | N SDR_BA0   |             |             |             |
+|  22 | N SDR_BA1   |             |             |             |
+|  23 | N SDR_CLK   |             |             |             |
+|  24 | N SDR_CKE   |             |             |             |
+|  25 | N SDR_RASn  |             |             |             |
+|  26 | N SDR_CASn  |             |             |             |
+|  27 | N SDR_WEn   |             |             |             |
+|  28 | N SDR_CSn0  |             |             |             |
+|  30 | N VSS_0     |             |             |             |
+|  31 | N VDD_0     |             |             |             |
+|  32 | E VSS_1     |             |             |             |
+|  33 | E SDR_SDRAD10 |             |             |             |
+|  34 | E SDR_SDRAD11 |             |             |             |
+|  35 | E SDR_SDRAD12 |             |             |             |
+|  36 | E SDR_DQM1  |             |             |             |
+|  37 | E SDR_D8    |             |             |             |
+|  38 | E SDR_D9    |             |             |             |
+|  39 | E SDR_D10   |             |             |             |
+|  40 | E SDR_D11   |             |             |             |
+|  41 | E SDR_D12   |             |             |             |
+|  42 | E SDR_D13   |             |             |             |
+|  43 | E SDR_D14   |             |             |             |
+|  44 | E SDR_D15   |             |             |             |
+|  45 | E VDD_1     |             |             |             |
+|  46 | E GPIOE_E8  |             |             |             |
+|  47 | E GPIOE_E9  |             |             |             |
+|  48 | E GPIOE_E10 |             |             |             |
+|  49 | E GPIOE_E11 |             |             |             |
+|  50 | E GPIOE_E12 |             |             |             |
+|  51 | E GPIOE_E13 |             |             |             |
+|  52 | E GPIOE_E14 |             |             |             |
+|  53 | E GPIOE_E15 |             |             |             |
+|  55 | E VSS_1     |             |             |             |
+|  56 | E JTAG_TMS  |             |             |             |
+|  57 | E JTAG_TDI  |             |             |             |
+|  58 | E JTAG_TDO  |             |             |             |
+|  59 | E JTAG_TCK  |             |             |             |
+|  63 | E VDD_1     |             |             |             |
+|  64 | S VSS_1     |             |             |             |
+|  65 | S CLK_0     |             |             |             |
+|  66 | S RST_0     |             |             |             |
+|  67 | S MSPI0_CK  |             |             |             |
+|  68 | S MSPI0_NSS |             |             |             |
+|  69 | S MSPI0_MOSI |             |             |             |
+|  70 | S MSPI0_MISO |             |             |             |
+|  71 | S UART0_TX  |             |             |             |
+|  72 | S UART0_RX  |             |             |             |
+|  95 | S VDD_1     |             |             |             |
+|  96 | W VSS_1     |             |             |             |
+|  97 | W PWM_0     |             |             |             |
+|  98 | W PWM_1     |             |             |             |
+|  99 | W EINT_0    |             |             |             |
+| 100 | W EINT_1    |             |             |             |
+| 101 | W EINT_2    |             |             |             |
+| 102 | W MSPI1_CK  |             |             |             |
+| 103 | W MSPI1_NSS |             |             |             |
+| 104 | W MSPI1_MOSI |             |             |             |
+| 105 | W MSPI1_MISO |             |             |             |
+| 106 | W MMC0_CMD  |             |             |             |
+| 107 | W MMC0_CLK  |             |             |             |
+| 108 | W MMC0_D0   |             |             |             |
+| 109 | W MMC0_D1   |             |             |             |
+| 110 | W MMC0_D2   |             |             |             |
+| 111 | W MMC0_D3   |             |             |             |
+| 127 | W VDD_1     |             |             |             |
+
+# Reference Datasheets
+
+datasheets and pinout links
+* <http://datasheets.chipdb.org/AMD/8018x/80186/amd-80186.pdf>
+* <http://hands.com/~lkcl/eoma/shenzen/frida/FRD144A2701.pdf>
+* <http://pinouts.ru/Memory/sdcard_pinout.shtml>
+* p8 <http://www.onfi.org/~/media/onfi/specs/onfi_2_0_gold.pdf?la=en>
+* <https://www.heyrick.co.uk/blog/files/datasheets/dm9000aep.pdf>
+* <http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4393.pdf>
+* <https://www.nxp.com/docs/en/data-sheet/MCF54418.pdf>
+* ULPI OTG PHY, ST <http://www.st.com/en/interfaces-and-transceivers/stulpi01a.html>
+* ULPI OTG PHY, TI TUSB1210 <http://ti.com/product/TUSB1210/>
+
+# Pin Bank starting points and lengths
+
+* E 32 32 2
+* N 0 32 2
+* S 64 32 2
+* W 96 32 2