sse.md (*vec_concatv2si_sse4_1): Add avx512dq v=Yv,rm alternative.

	* config/i386/sse.md (*vec_concatv2si_sse4_1): Add avx512dq v=Yv,rm
	alternative.  Change x=x,x alternative to v=Yv,Yv and x=rm,C
	alternative to v=rm,C.

	* gcc.target/i386/avx512dq-concatv2si-1.c: New test.
	* gcc.target/i386/avx512vl-concatv2si-1.c: New test.

From-SVN: r237030

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ed739918191168a31b1bfe1e2d74d0759595962f..bff651298429babd426973d7d34c917d58c41f87 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2016-06-02  Jakub Jelinek  <jakub@redhat.com>
 
+       * config/i386/sse.md (*vec_concatv2si_sse4_1): Add avx512dq v=Yv,rm
+       alternative.  Change x=x,x alternative to v=Yv,Yv and x=rm,C
+       alternative to v=rm,C.
+
        * config/i386/sse.md (*vec_concatv2di): Add x86_avx512dq v=Yv,rm
        alternative.  Change x=xm,C alternative to v=vm,C, x=x,x alternative
        to v=Yv,Yv and x=x,m to v=v,m.  Use maybe_evex prefix attribute

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 22543abc6be7c487231fd4d8c500dd59a9169798..2a11887adb019297bfb04e773b1fdaf4b5b849e9 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13488,43 +13488,44 @@
 
 (define_insn "*vec_concatv2si_sse4_1"
   [(set (match_operand:V2SI 0 "register_operand"
-         "=Yr,*x,x, Yr,*x,x, x, *y,*y")
+         "=Yr,*x, x, v,Yr,*x, v, v, *y,*y")
        (vec_concat:V2SI
          (match_operand:SI 1 "nonimmediate_operand"
-         "  0, 0,x,  0,0, x,rm,  0,rm")
+         "  0, 0, x,Yv, 0, 0,Yv,rm,  0,rm")
          (match_operand:SI 2 "vector_move_operand"
-         " rm,rm,rm,Yr,*x,x, C,*ym, C")))]
+         " rm,rm,rm,rm,Yr,*x,Yv, C,*ym, C")))]
   "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "@
    pinsrd\t{$1, %2, %0|%0, %2, 1}
    pinsrd\t{$1, %2, %0|%0, %2, 1}
    vpinsrd\t{$1, %2, %1, %0|%0, %1, %2, 1}
+   vpinsrd\t{$1, %2, %1, %0|%0, %1, %2, 1}
    punpckldq\t{%2, %0|%0, %2}
    punpckldq\t{%2, %0|%0, %2}
    vpunpckldq\t{%2, %1, %0|%0, %1, %2}
    %vmovd\t{%1, %0|%0, %1}
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
-  [(set_attr "isa" "noavx,noavx,avx,noavx,noavx,avx,*,*,*")
+  [(set_attr "isa" "noavx,noavx,avx,avx512dq,noavx,noavx,avx,*,*,*")
    (set (attr "type")
-     (cond [(eq_attr "alternative" "6")
+     (cond [(eq_attr "alternative" "7")
              (const_string "ssemov")
-           (eq_attr "alternative" "7")
-             (const_string "mmxcvt")
            (eq_attr "alternative" "8")
+             (const_string "mmxcvt")
+           (eq_attr "alternative" "9")
              (const_string "mmxmov")
           ]
           (const_string "sselog")))
    (set (attr "prefix_extra")
-     (if_then_else (eq_attr "alternative" "0,1,2")
+     (if_then_else (eq_attr "alternative" "0,1,2,3")
                   (const_string "1")
                   (const_string "*")))
    (set (attr "length_immediate")
-     (if_then_else (eq_attr "alternative" "0,1,2")
+     (if_then_else (eq_attr "alternative" "0,1,2,3")
                   (const_string "1")
                   (const_string "*")))
-   (set_attr "prefix" "orig,orig,vex,orig,orig,vex,maybe_vex,orig,orig")
-   (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,DI,DI")])
+   (set_attr "prefix" "orig,orig,vex,evex,orig,orig,maybe_evex,maybe_vex,orig,orig")
+   (set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,TI,DI,DI")])
 
 ;; ??? In theory we can match memory for the MMX alternative, but allowing
 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 79554ec4b92535c22fc8a737cb67123adbf63a09..3d279fdbf036a17946d96effe3fffa270e2c1408 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,8 @@
 2016-06-02  Jakub Jelinek  <jakub@redhat.com>
 
+       * gcc.target/i386/avx512dq-concatv2si-1.c: New test.
+       * gcc.target/i386/avx512vl-concatv2si-1.c: New test.
+
        * gcc.target/i386/avx512dq-concatv2di-1.c: New test.
        * gcc.target/i386/avx512vl-concatv2di-1.c: New test.
        * gcc.target/i386/sse2-init-v2di-2.c: Adjust expected vec_concatv2di

diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-concatv2si-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-concatv2si-1.c
new file mode 100644 (file)
index 0000000..bb5e42f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-concatv2si-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mavx512dq -masm=att" } */
+
+typedef int V __attribute__((vector_size (8)));
+
+void
+f1 (int x, int y)
+{
+  register int a __asm ("xmm16");
+  register int b __asm ("xmm17");
+  register V c __asm ("xmm3");
+  a = x;
+  b = y;
+  asm volatile ("" : "+v" (a), "+v" (b));
+  c = (V) { a, b };
+  asm volatile ("" : "+v" (c));
+}
+
+/* { dg-final { scan-assembler "vpunpckldq\[^\n\r]*%xmm17\[^\n\r]*%xmm16\[^\n\r]*%xmm3" } } */
+
+void
+f2 (int x, int y)
+{
+  register int a __asm ("xmm16");
+  register V c __asm ("xmm3");
+  a = x;
+  asm volatile ("" : "+v" (a));
+  c = (V) { a, y };
+  asm volatile ("" : "+v" (c));
+}
+
+void
+f3 (int x, int *y)
+{
+  register int a __asm ("xmm16");
+  register V c __asm ("xmm3");
+  a = x;
+  asm volatile ("" : "+v" (a));
+  c = (V) { a, *y };
+  asm volatile ("" : "+v" (c));
+}
+
+/* { dg-final { scan-assembler-times "vpinsrd\[^\n\r]*\\\$1\[^\n\r]*%xmm16\[^\n\r]*%xmm3" 2 } } */

diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-concatv2si-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-concatv2si-1.c
new file mode 100644 (file)
index 0000000..6ac293d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-concatv2si-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mno-avx512dq -masm=att" } */
+
+typedef int V __attribute__((vector_size (8)));
+
+void
+f1 (int x, int y)
+{
+  register int a __asm ("xmm16");
+  register int b __asm ("xmm17");
+  register V c __asm ("xmm3");
+  a = x;
+  b = y;
+  asm volatile ("" : "+v" (a), "+v" (b));
+  c = (V) { a, b };
+  asm volatile ("" : "+v" (c));
+}
+
+/* { dg-final { scan-assembler "vpunpckldq\[^\n\r]*%xmm17\[^\n\r]*%xmm16\[^\n\r]*%xmm3" } } */
+
+void
+f2 (int x, int y)
+{
+  register int a __asm ("xmm16");
+  register V c __asm ("xmm3");
+  a = x;
+  asm volatile ("" : "+v" (a));
+  c = (V) { a, y };
+  asm volatile ("" : "+v" (c));
+}
+
+void
+f3 (int x, int *y)
+{
+  register int a __asm ("xmm16");
+  register V c __asm ("xmm3");
+  a = x;
+  asm volatile ("" : "+v" (a));
+  c = (V) { a, *y };
+  asm volatile ("" : "+v" (c));
+}
+
+/* { dg-final { scan-assembler-not "vpinsrd\[^\n\r]*\\\$1\[^\n\r]*%xmm16\[^\n\r]*%xmm3" } } */