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arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 2 Sep 2019 14:28:58 +0000 (15:28 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 6 Sep 2019 20:00:34 +0000 (20:00 +0000)
Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/miscregs.cc patch | blob | history

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 0bae0189311d8d144010a53d4a69eeea0df66139..76a991746fa7513c546907115952391276caf0af 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4603,7 +4603,7 @@ ISA::initializeMiscRegMetadata()
         .allPrivileges().exceptUserMode().writes(0)
         .mapsTo(MISCREG_ICC_HPPIR1);
     InitReg(MISCREG_ICC_BPR1_EL1)
-        .banked()
+        .banked64()
         .mapsTo(MISCREG_ICC_BPR1);
     InitReg(MISCREG_ICC_BPR1_EL1_NS)
         .bankedChild()