* **Zero-Level**: Simple-V is not implemented (at all) in hardware. This
Level is required to be listed because all capabilities of Simple-V
- must be Soft-emulatable.
-* **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
- to/from SVSRR1. Register Files as Standard Power ISA. `scalar identity`
- implemented.
+ must be Soft-emulatable by way of Illegal Instruction Traps.
+* **Ultra-embedded**: `setvl` instruction. Register Files as Standard Power
+ ISA. `scalar identity behaviour` implemented.
* **Embedded**: `svstep` instruction,
and support for Hardware for-looping
in both Horizontal-First and Vertical-First Mode as well as Predication