[arm] Convert gcc.target/arm/stl-cond.c into an RTL test

This is an awkward testsuite failure. The original bug was that we were failing to put out
the conditional code in the conditional form of the STL instruction (oops!).
So we wanted to output STLNE, but instead output STL.
The testacase relies on if-conversion to conditionalise the insn for STL.
However, ever since r251643 the expansion of a non-relaxed atomic store
always includes a compiler barrier. That blocks if-conversion in all cases.

So there's no easy way to get to a conditional STL instruction from a C program.
But we do want to test for the original bug fix that if the RTL insn for STL is conditionalised
it should output the conditional code.

The solution in this patch is to convert the test into an RTL test with the COND_EXEC form
of the STL insn and scan the assembly output there.
This seems to work fine, and gives us an opportunity to create a gcc.dg/rtl/arm directory
in the RTL tests.

This now makes the gcc.target/arm/stl-cond.c disappear (as the test is deleted) and
the new test in gcc.dg/rtl/arm/stl-cond.c passes.

     * gcc.dg/rtl/arm/stl-cond.c: New test.
     * gcc.target/arm/stl-cond.c: Delete.

From-SVN: r256785

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 43d1a90bf90f4f73eea099f5a9738dfa00af1b6d..be4bece36636075392dd47daca1a9afa5d015631 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * gcc.dg/rtl/arm/stl-cond.c: New test.
+       * gcc.target/arm/stl-cond.c: Delete.
+
 2018-01-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * gcc.target/arm/pr40887.c: Add armv5te effective target checks and

diff --git a/gcc/testsuite/gcc.dg/rtl/arm/stl-cond.c b/gcc/testsuite/gcc.dg/rtl/arm/stl-cond.c
new file mode 100644 (file)
index 0000000..e2bc610
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/rtl/arm/stl-cond.c
@@ -0,0 +1,61 @@
+/* { dg-do compile { target arm-*-* } } */
+/* { dg-require-effective-target arm_arm_ok } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2 -marm" } */
+/* { dg-add-options arm_arch_v8a } */
+
+/* We want to test that the STL instruction gets the conditional
+   suffix when under a COND_EXEC.  However, COND_EXEC is very hard to
+   generate from C code because the atomic_store expansion adds a compiler
+   barrier before the insn, preventing if-conversion.  So test the output
+   here with a hand-crafted COND_EXEC wrapped around an STL.  */
+
+void __RTL (startwith ("final")) foo (int *a, int b)
+{
+(function "foo"
+  (param "a"
+    (DECL_RTL (reg/v:SI r0))
+    (DECL_RTL_INCOMING (reg:SI r0))
+  )
+  (param "b"
+    (DECL_RTL (reg/v:SI r1))
+    (DECL_RTL_INCOMING (reg:SI r1))
+  )
+  (insn-chain
+    (block 2
+       (edge-from entry (flags "FALLTHRU"))
+       (cnote 5 [bb 2] NOTE_INSN_BASIC_BLOCK)
+
+  (insn:TI 7 (parallel [
+       (set (reg:CC cc)
+            (compare:CC (reg:SI r1)
+                        (const_int 0)))
+       (set (reg/v:SI r1)
+            (reg:SI r1 ))
+        ])  ;; {*movsi_compare0}
+     (nil))
+
+  ;; A conditional atomic store-release: STLNE for Armv8-A.
+  (insn 10 (cond_exec (ne (reg:CC cc)
+          (const_int 0))
+       (set (mem/v:SI (reg/v/f:SI r0) [-1  S4 A32])
+               (unspec_volatile:SI [
+               (reg/v:SI r1)
+               (const_int 3)
+               ] VUNSPEC_STL))) ;; {*p atomic_storesi}
+       (expr_list:REG_DEAD (reg:CC cc)
+       (expr_list:REG_DEAD (reg/v:SI r1)
+       (expr_list:REG_DEAD (reg/v/f:SI r0)
+               (nil)))))
+      (edge-to exit (flags "FALLTHRU"))
+    ) ;; block 2
+  ) ;; insn-chain
+  (crtl
+    (return_rtx
+      (reg/i:SI r0)
+    ) ;; return_rtx
+  ) ;; crtl
+) ;; function
+}
+
+/* { dg-final { scan-assembler "stlne" } } */

diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c
deleted file mode 100644 (file)
index de14bb5..0000000
--- a/gcc/testsuite/gcc.target/arm/stl-cond.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target arm_arm_ok } */ 
-/* { dg-require-effective-target arm_arch_v8a_ok } */
-/* { dg-options "-O2 -marm" } */
-/* { dg-add-options arm_arch_v8a } */
-
-struct backtrace_state
-{
-  int threaded;
-  int lock_alloc;
-};
-
-void foo (struct backtrace_state *state)
-{
-  if (state->threaded)
-    __sync_lock_release (&state->lock_alloc);
-}
-
-/* { dg-final { scan-assembler "stlne" } } */