ppc: support ternlogi instructions

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 5da429e1a802139806f040e860cbe2223078081b..a0e3483731ace920417482306cd63c6848673252 100644 (file)
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -180,3 +180,4 @@ run_dump_test "ffmadds"
 run_dump_test "ffnmsubs"
 run_dump_test "ffnmadds"
 run_dump_test "fdmadds"
+run_dump_test "ternlogi"

diff --git a/gas/testsuite/gas/ppc/ternlogi.d b/gas/testsuite/gas/ppc/ternlogi.d
new file mode 100644 (file)
index 0000000..96405b0
--- /dev/null
+++ b/gas/testsuite/gas/ppc/ternlogi.d
@@ -0,0 +1,25 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:\s+(17 e0 00 00|00 00 e0 17)\s+ternlogi\s+r31,r0,r0,0
+.*:\s+(14 1f 00 00|00 00 1f 14)\s+ternlogi\s+r0,r31,r0,0
+.*:\s+(14 00 f8 00|00 f8 00 14)\s+ternlogi\s+r0,r0,r31,0
+.*:\s+(14 00 07 f8|f8 07 00 14)\s+ternlogi\s+r0,r0,r0,255
+.*:\s+(17 e0 00 01|01 00 e0 17)\s+ternlogi.\s+r31,r0,r0,0
+.*:\s+(14 1f 00 01|01 00 1f 14)\s+ternlogi.\s+r0,r31,r0,0
+.*:\s+(14 00 f8 01|01 f8 00 14)\s+ternlogi.\s+r0,r0,r31,0
+.*:\s+(14 00 07 f9|f9 07 00 14)\s+ternlogi.\s+r0,r0,r0,255
+.*:\s+(17 80 00 02|02 00 80 17)\s+crfternlogi\s+cr7,cr0,cr0,0,0
+.*:\s+(14 1c 00 02|02 00 1c 14)\s+crfternlogi\s+cr0,cr7,cr0,0,0
+.*:\s+(14 00 e0 02|02 e0 00 14)\s+crfternlogi\s+cr0,cr0,cr7,0,0
+.*:\s+(14 00 1f c3|c3 1f 00 14)\s+crfternlogi\s+cr0,cr0,cr0,255,0
+.*:\s+(14 63 00 02|02 00 63 14)\s+crfternlogi\s+cr0,cr0,cr0,0,15
+.*:\s+(17 e0 00 06|06 00 e0 17)\s+crternlogi\s+4\*cr7\+so,lt,lt,0
+.*:\s+(14 1f 00 06|06 00 1f 14)\s+crternlogi\s+lt,4\*cr7\+so,lt,0
+.*:\s+(14 00 f8 06|06 f8 00 14)\s+crternlogi\s+lt,lt,4\*cr7\+so,0
+.*:\s+(14 00 07 fe|fe 07 00 14)\s+crternlogi\s+lt,lt,lt,255

diff --git a/gas/testsuite/gas/ppc/ternlogi.s b/gas/testsuite/gas/ppc/ternlogi.s
new file mode 100644 (file)
index 0000000..46e630d
--- /dev/null
+++ b/gas/testsuite/gas/ppc/ternlogi.s
@@ -0,0 +1,17 @@
+ternlogi 31,0,0,0
+ternlogi 0,31,0,0
+ternlogi 0,0,31,0
+ternlogi 0,0,0,255
+ternlogi. 31,0,0,0
+ternlogi. 0,31,0,0
+ternlogi. 0,0,31,0
+ternlogi. 0,0,0,255
+crfternlogi 7,0,0,0,0
+crfternlogi 0,7,0,0,0
+crfternlogi 0,0,7,0,0
+crfternlogi 0,0,0,255,0
+crfternlogi 0,0,0,0,15
+crternlogi 31,0,0,0
+crternlogi 0,31,0,0
+crternlogi 0,0,31,0
+crternlogi 0,0,0,255

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index d168258374fa3b6d683304c9c46c4a25bc2626bb..79900746b23648990cf04ddfca6300ce846f5def 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2846,6 +2846,47 @@ extract_SVrm (uint64_t insn,
   return value;
 }
 
+static uint64_t
+insert_CRFTLIF (uint64_t insn,
+            int64_t value,
+            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if ((value < 0) || (value > 255))
+    *errmsg = _("invalid TLI value");
+  return insn | ((value & 0x1f) << 6) | ((value & 0x3) << 11) | ((value & 0x1) << 0);
+}
+
+static int64_t
+extract_CRFTLIF (uint64_t insn,
+             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((((insn >> 6) & 0x1f) << 3) |
+    (((insn >> 11) & 0x3) << 1) |
+    (((insn >> 0) & 0x1) << 0));
+}
+
+static uint64_t
+insert_CRFTLIM (uint64_t insn,
+            int64_t value,
+            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if ((value < 0) || (value > 15))
+    *errmsg = _("invalid mask value");
+  return insn | ((value & 0x3) << 21) | ((value & 0x3) << 16);
+}
+
+static int64_t
+extract_CRFTLIM (uint64_t insn,
+             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((((insn >> 21) & 0x3) << 2) |
+    (((insn >> 16) & 0x3) << 0));
+}
+
 \f
 /* The operands table.
 
@@ -4040,6 +4081,18 @@ const struct powerpc_operand powerpc_operands[] =
 
 #define MMM FMM + 1
   { 0x7, 8, NULL, NULL, 0 },
+
+#define TLIF MMM + 1
+  { 0xff, 3, NULL, NULL, 0 },
+
+#define CRFTLIF TLIF + 1
+  { 0xff, PPC_OPSHIFT_INV, insert_CRFTLIF, extract_CRFTLIF, 0 },
+
+#define CRFTLIM CRFTLIF + 1
+  { 0xf, PPC_OPSHIFT_INV, insert_CRFTLIM, extract_CRFTLIM, 0 },
+
+#define BFB CRFTLIM + 1
+  { 0x7, 13, NULL, NULL, PPC_OPERAND_CR_REG },
 };
 
 const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
@@ -4985,6 +5038,32 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
    | (((uint64_t)(rc)) & 1))
 #define MMXMMM_MASK    MMXMMM (0x3f, 0x3f, 0x7, 0x1)
 
+/* An MM form instruction with explicit FMM. */
+#define MMXFMM(op, xop, fmm, rc)               \
+  (OP (op)                                     \
+   | ((((uint64_t)(fmm)) & 0xf) << 7)          \
+   | ((((uint64_t)(xop)) & 0x3f) << 1)         \
+   | (((uint64_t)(rc)) & 1))
+#define MMXFMM_MASK    MMXFMM (0x3f, 0x3f, 0xf, 0x1)
+
+/* An TLI form instructions */
+#define TLI(op, xop, rc)                       \
+  (OP (op)                                     \
+   | ((((uint64_t)(xop)) & 0x3) << 1)          \
+   | (((uint64_t)(rc)) & 1))
+
+#define CRFTLI(op, xop)                                \
+  (OP (op)                                     \
+   | ((((uint64_t)(xop)) & 0x1f) << 1))
+
+#define CRTLI(op, xop)                         \
+  (OP (op)                                     \
+   | ((((uint64_t)(xop)) & 0x3) << 1))
+
+#define TLI_MASK       TLI(0x3f, 0x3, 1)
+#define CRFTLI_MASK    CRFTLI(0x3f, 0x1f)
+#define CRTLI_MASK     CRTLI(0x3f, 0x3)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF (0x0)
 #define BODNZFP        (0x1)
@@ -6145,6 +6224,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
 {"dcbz_l",     X  (4,1014),    XRT_MASK,    PPCPS,     0,              {RA, RB}},
 
+{"ternlogi",   TLI(5,0,0),     TLI_MASK,       SFFS,   PPCVLE,         {RT, RA, RB, TLIF}},
+{"ternlogi.",  TLI(5,0,1),     TLI_MASK,       SFFS,   PPCVLE,         {RT, RA, RB, TLIF}},
+{"crfternlogi",        CRFTLI(5,1),    CRFTLI_MASK,    SFFS,   PPCVLE,         {BF, BFA, BFB, CRFTLIF, CRFTLIM}},
+{"crternlogi", CRTLI(5,3),     CRTLI_MASK,     SFFS,   PPCVLE,         {BT, BA, BB, TLIF}},
+
 {"lxvp",       DQXP(6,0),      DQXP_MASK,   POWER10,   PPCVLE,         {XTP, DQ, RA0}},
 {"stxvp",      DQXP(6,1),      DQXP_MASK,   POWER10,   PPCVLE,         {XSP, DQ, RA0}},