+2004-08-12 Andrew Pinski <pinskia@physics.uc.edu>
+
+ * config/darwin-c.c (find_subframework_file): Fix spelling of cannot.
+ * config/libgloss.h: Likewise.
+ * config/arm/arm.c (arm_gen_load_multiple): Likewise.
+ * c4x/c4x-modes.def: Likewise.
+ * config/c4x/c4x.c (c4x_hard_regno_rename_ok): Likewise.
+ (c4x_rptb_nop_p): Likewise.
+ (c4x_rptb_valid_p): Likewise.
+ (c4x_rptb_insert): Likewise.
+ (c4x_address_conflict): Likewise.
+ * config/c4x/c4x.md: Likewise.
+ * config/frv/frv.md: Likewise.
+ * config/i386/athlon.md: Likewise.
+ * config/i386/i386.md: Likewise.
+ * config/i386/predicates.md: Likewise.
+ * config/ia64/ia64.c: Likewise.
+ * config/ia64/itanium1.md: Likewise.
+ * config/ia64/itanium2.md: Likewise.
+ * config/iq2000/iq2000.md: Likewise.
+ * config/mcore/mcore.c: Likewise.
+ * config/mips/mips.c: Likewise.
+ * config/mips/r3900.h: Likewise.
+ * config/mips/sb1.md: Likewise.
+ * config/pa/milli64.S: Likewise.
+ * config/pa/pa.c: Likewise.
+ * config/pa/pa.h: Likewise.
+ * config/rs6000/8540.md: Likewise.
+
2004-08-13 Daniel Berlin <dberlin@dberlin.org>
* Makefile.in (BOOT_CFLAGS): Remove accidental addition of -dU.
rtx mem;
/* XScale has load-store double instructions, but they have stricter
- alignment requirements than load-store multiple, so we can not
+ alignment requirements than load-store multiple, so we cannot
use them.
For XScale ldm requires 2 + NREGS cycles to complete and blocks
Thus (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000))) sets the N
flag but (GE (0x00000001)) does not set the N flag.
- The upshot is that we can not use signed branch and conditional
+ The upshot is that we cannot use signed branch and conditional
load instructions after an add, subtract, neg, abs or multiply.
We must emit a compare insn to check the result against 0. */
int
c4x_hard_regno_rename_ok (unsigned int regno1, unsigned int regno2)
{
- /* We can not copy call saved registers from mode QI into QF or from
+ /* We cannot copy call saved registers from mode QI into QF or from
mode QF into QI. */
if (IS_FLOAT_CALL_SAVED_REGNO (regno1) && IS_INT_CALL_SAVED_REGNO (regno2))
return 0;
Before we can create a repeat block looping instruction we have to
verify that there are no jumps outside the loop and no jumps outside
the loop go into this loop. This can happen in the basic blocks reorder
- pass. The C4x cpu can not handle this. */
+ pass. The C4x cpu cannot handle this. */
static int
c4x_label_ref_used_p (rtx x, rtx code_label)
if (insn == start_label)
break;
- /* Note found then we can not use a rptb or rpts. The label was
+ /* Note found then we cannot use a rptb or rpts. The label was
probably moved by the basic block reorder pass. */
if (! insn)
return 0;
if (! c4x_rptb_valid_p (insn, start_label))
{
- /* We can not use the rptb insn. Replace it so reorg can use
+ /* We cannot use the rptb insn. Replace it so reorg can use
the delay slots of the jump insn. */
emit_insn_before (gen_addqi3 (count_reg, count_reg, constm1_rtx), insn);
emit_insn_before (gen_cmpqi (count_reg, const0_rtx), insn);
if (! TARGET_DEVEL && base0 == base1 && (incdec0 || incdec1))
return 1;
- /* We can not optimize the case where op1 and op2 refer to the same
+ /* We cannot optimize the case where op1 and op2 refer to the same
address. */
if (base0 == base1 && disp0 == disp1 && index0 == index1)
return 1;
; op3 fetch executed
; This means that we can allow any instruction in the last delay slot
; and only instructions which modify registers in the first two.
-; lda can not be executed in the first delay slot
-; and ldpk can not be executed in the first two delay slots.
+; lda cannot be executed in the first delay slot
+; and ldpk cannot be executed in the first two delay slots.
(define_attr "onlyreg" "false,true"
(cond [(eq_attr "type" "unary,unarycc")
"push\\t%0"
[(set_attr "type" "push")])
-; we can not use this because the popf will destroy the low 8 bits
+; we cannot use this because the popf will destroy the low 8 bits
;(define_insn "pophf"
; [(set (match_operand:HF 0 "reg_operand" "=h")
; (mem:HF (post_dec:QI (reg:QI 20))))
bufptr = strstr (pname, dot_framework);
/* If the parent header is not of any framework, then this header
- can not be part of any subframework. */
+ cannot be part of any subframework. */
if (!bufptr)
return 0;
DEFINE_AUTOMATON).
All define_reservations and define_cpu_units should have unique
- names which can not be "nothing".
+ names which cannot be "nothing".
o (exclusion_set string string) means that each CPU function unit
- in the first string can not be reserved simultaneously with each
+ in the first string cannot be reserved simultaneously with each
unit whose name is in the second string and vise versa. CPU
units in the string are separated by commas. For example, it is
useful for description CPU with fully pipelined floating point
floating point insns or only double floating point insns.
o (presence_set string string) means that each CPU function unit in
- the first string can not be reserved unless at least one of units
+ the first string cannot be reserved unless at least one of units
whose names are in the second string is reserved. This is an
asymmetric relation. CPU units in the string are separated by
commas. For example, it is useful for description that slot1 is
reserved after slot0 reservation for a VLIW processor.
o (absence_set string string) means that each CPU function unit in
- the first string can not be reserved only if each unit whose name
+ the first string cannot be reserved only if each unit whose name
is in the second string is not reserved. This is an asymmetric
relation (actually exclusion set is analogous to this one but it
is symmetric). CPU units in the string are separated by commas.
- For example, it is useful for description that slot0 can not be
+ For example, it is useful for description that slot0 cannot be
reserved after slot1 or slot2 reservation for a VLIW processor.
o (define_bypass number out_insn_names in_insn_names) names bypass with
case, you describe common part and use one its name (the 1st
parameter) in regular expression in define_insn_reservation. All
define_reservations, define results and define_cpu_units should
- have unique names which can not be "nothing".
+ have unique names which cannot be "nothing".
o (define_insn_reservation name default_latency condition regexpr)
describes reservation of cpu functional units (the 3nd operand)
return 1;
/* Accept any mem during RTL generation. Otherwise, the code that does
- insv and extzv will think that we can not handle memory. However,
+ insv and extzv will think that we cannot handle memory. However,
to avoid reload problems, we only accept 'U' MEM operands after RTL
generation. This means that any named pattern which uses this predicate
must force its operands to match 'U' before emitting RTL. */
(eq_attr "memory" "load,both")))
"athlon-vector,athlon-load,athlon-ieu,athlon-mult,athlon-ieu")
-;; Idiv can not execute in parallel with other instructions. Dealing with it
+;; Idiv cannot execute in parallel with other instructions. Dealing with it
;; as with short latency vector instruction is good approximation avoiding
;; scheduler from trying too hard to can hide it's latency by overlap with
;; other instructions.
[(set_attr "type" "idiv")
(set_attr "mode" "HI")])
-;; We can not use div/idiv for double division, because it causes
+;; We cannot use div/idiv for double division, because it causes
;; "division by zero" on the overflow and that's not what we expect
;; from truncate. Because true (non truncating) double division is
;; never generated, we can't create this insn anyway.
;; Don't split NOTs with a displacement operand, because resulting XOR
;; will not be pairable anyway.
;;
-;; On AMD K6, NOT is vector decoded with memory operand that can not be
+;; On AMD K6, NOT is vector decoded with memory operand that cannot be
;; represented using a modRM byte. The XOR replacement is long decoded,
;; so this split helps here as well.
;;
;; TImode, since backend insist on eliminating casts
;; on memory operands
;; sse_andti3_sf_1 - the operation taking SF scalar operands.
-;; We can not accept memory operand here as instruction reads
+;; We cannot accept memory operand here as instruction reads
;; whole scalar. This is generated only post reload by GCC
;; scalar float operations that expands to logicals (fabs)
;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
return parts.disp != NULL_RTX;
})
-;; Returns 1 if OP is memory operand that can not be represented
+;; Returns 1 if OP is memory operand that cannot be represented
;; by the modRM array.
(define_predicate "long_memory_operand"
(and (match_operand 0 "memory_operand")
}
/* For all ASM_OPERANDS, we must traverse the vector of input operands.
- We can not just fall through here since then we would be confused
+ We cannot just fall through here since then we would be confused
by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
traditional asms unlike their normal usage. */
static rtx dfa_pre_cycle_insn;
-/* We are about to being issuing INSN. Return nonzero if we can not
+/* We are about to being issuing INSN. Return nonzero if we cannot
issue it on given cycle CLOCK and return zero if we should not sort
the ready queue on the next clock start. */
by structure bundle_state (see above). If we generate the same
bundle state (key is automaton state after issuing the insns and
nops for it), we reuse already generated one. As consequence we
- reject some decisions which can not improve the solution and
+ reject some decisions which cannot improve the solution and
reduce memory for the algorithm.
When we reach the end of EBB (extended basic block), we choose the
DEFINE_AUTOMATON).
All define_reservations and define_cpu_units should have unique
- names which can not be "nothing".
+ names which cannot be "nothing".
o (exclusion_set string string) means that each CPU function unit
- in the first string can not be reserved simultaneously with each
+ in the first string cannot be reserved simultaneously with each
unit whose name is in the second string and vise versa. CPU
units in the string are separated by commas. For example, it is
useful for description CPU with fully pipelined floating point
floating point insns or only double floating point insns.
o (presence_set string string) means that each CPU function unit in
- the first string can not be reserved unless at least one of
+ the first string cannot be reserved unless at least one of
pattern of units whose names are in the second string is
reserved. This is an asymmetric relation. CPU units or unit
patterns in the strings are separated by commas. Pattern is one
string are separated by commas. Pattern is one unit name or unit
names separated by white-spaces.
- For example, it is useful for description that slot0 can not be
+ For example, it is useful for description that slot0 cannot be
reserved after slot1 or slot2 reservation for a VLIW processor.
We could describe it by the following construction
(absence_set "slot2" "slot0, slot1")
- Or slot2 can not be reserved if slot0 and unit b0 are reserved or
+ Or slot2 cannot be reserved if slot0 and unit b0 are reserved or
slot1 and unit b1 are reserved . In this case we could write
(absence_set "slot2" "slot0 b0, slot1 b1")
case, you describe common part and use one its name (the 1st
parameter) in regular expression in define_insn_reservation. All
define_reservations, define results and define_cpu_units should
- have unique names which can not be "nothing".
+ have unique names which cannot be "nothing".
o (define_insn_reservation name default_latency condition regexpr)
describes reservation of cpu functional units (the 3nd operand)
DEFINE_AUTOMATON).
All define_reservations and define_cpu_units should have unique
- names which can not be "nothing".
+ names which cannot be "nothing".
o (exclusion_set string string) means that each CPU function unit
- in the first string can not be reserved simultaneously with each
+ in the first string cannot be reserved simultaneously with each
unit whose name is in the second string and vise versa. CPU
units in the string are separated by commas. For example, it is
useful for description CPU with fully pipelined floating point
floating point insns or only double floating point insns.
o (presence_set string string) means that each CPU function unit in
- the first string can not be reserved unless at least one of
+ the first string cannot be reserved unless at least one of
pattern of units whose names are in the second string is
reserved. This is an asymmetric relation. CPU units or unit
patterns in the strings are separated by commas. Pattern is one
string are separated by commas. Pattern is one unit name or unit
names separated by white-spaces.
- For example, it is useful for description that slot0 can not be
+ For example, it is useful for description that slot0 cannot be
reserved after slot1 or slot2 reservation for a VLIW processor.
We could describe it by the following construction
(absence_set "slot2" "slot0, slot1")
- Or slot2 can not be reserved if slot0 and unit b0 are reserved or
+ Or slot2 cannot be reserved if slot0 and unit b0 are reserved or
slot1 and unit b1 are reserved . In this case we could write
(absence_set "slot2" "slot0 b0, slot1 b1")
case, you describe common part and use one its name (the 1st
parameter) in regular expression in define_insn_reservation. All
define_reservations, define results and define_cpu_units should
- have unique names which can not be "nothing".
+ have unique names which cannot be "nothing".
o (define_insn_reservation name default_latency condition regexpr)
describes reservation of cpu functional units (the 3nd operand)
"2_stop")
;; The issue logic can reorder M slot insns between different subtypes
-;; but can not reorder insn within the same subtypes. The following
+;; but cannot reorder insn within the same subtypes. The following
;; constraint is enough to describe this.
(final_presence_set "2_um1" "2_um0")
(final_presence_set "2_um3" "2_um2")
"2b_stop")
;; The issue logic can reorder M slot insns between different subtypes
-;; but can not reorder insn within the same subtypes. The following
+;; but cannot reorder insn within the same subtypes. The following
;; constraint is enough to describe this.
(final_presence_set "2b_um1" "2b_um0")
(final_presence_set "2b_um3" "2b_um2")
\f
;; For the rare case where we need to load an address into a register
-;; that can not be recognized by the normal movsi/addsi instructions.
+;; that cannot be recognized by the normal movsi/addsi instructions.
;; I have no idea how many insns this can actually generate. It should
;; be rare, so over-estimating as 10 instructions should not have any
;; real performance impact.
/* This file used to force LINK_SPEC to be the null string, but that is not
correct. LINK_SPEC is used to pass machine specific arguments to the
- linker and hence can not be redefined here. LINK_SPEC is never used to
+ linker and hence cannot be redefined here. LINK_SPEC is never used to
specify startup files or libraries, so it should never conflict with
libgloss. */
}
}
- /* No conclusive evidence either way, we can not take the chance
+ /* No conclusive evidence either way, we cannot take the chance
that control flow hid the use from us -- "I'm not dead yet". */
return 0;
}
(exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
(exclusion_set "fxuf_mpy" "fxuf_divsqrt")
-;; After branch any insn can not be issued.
+;; After branch any insn cannot be issued.
(absence_set "rm7_iss0,rm7_iss1" "ixuf_branch")
;;
if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
target_flags |= MASK_VR4130_ALIGN;
- /* When compiling for the mips16, we can not use floating point. We
+ /* When compiling for the mips16, we cannot use floating point. We
record the original hard float value in mips16_hard_float. */
if (TARGET_MIPS16)
{
ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
/* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
- within a .ent, and we can not emit another .ent. */
+ within a .ent, and we cannot emit another .ent. */
if (!FUNCTION_NAME_ALREADY_DECLARED)
{
fputs ("\t.ent\t", file);
Fortunately, this case is illegal, since it means that a function
was declared in two different ways in a single compilation. */
if (fpret && ! l->fpret)
- error ("can not handle inconsistent calls to `%s'", fnname);
+ error ("cannot handle inconsistent calls to `%s'", fnname);
/* If we are calling a stub which handles a floating point return
value, we need to arrange to save $18 in the prologue. We do
#define SUBTARGET_CC1_SPEC "\
%{mhard-float:%e-mhard-float not supported} \
%{msingle-float:%{msoft-float: \
- %e-msingle-float and -msoft-float can not both be specified}}"
+ %e-msingle-float and -msoft-float cannot both be specified}}"
;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding
;; store data), otherwise a latency of 1 cycle.
-;; ??? We can not handle latencies properly for simple alu instructions
+;; ??? We cannot handle latencies properly for simple alu instructions
;; within the DFA pipeline model. Latencies can be defined only from one
;; insn reservation to another. We can't make them depend on which function
;; unit was used. This isn't a DFA flaw. There is a conflict here, as we
.export $$divI_3,millicode
comb,<,N x2,0,LREF(neg3)
- addi 1,x2,x2 /* this can not overflow */
+ addi 1,x2,x2 /* this cannot overflow */
extru x2,1,2,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(pos)
addc x1,0,x1
LSYM(neg3)
- subi 1,x2,x2 /* this can not overflow */
+ subi 1,x2,x2 /* this cannot overflow */
extru x2,1,2,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(neg)
.export $$divI_5,millicode
comb,<,N x2,0,LREF(neg5)
- addi 3,x2,t1 /* this can not overflow */
+ addi 3,x2,t1 /* this cannot overflow */
sh1add x2,t1,x2 /* multiply by 3 to get started */
b LREF(pos)
addc 0,0,x1
LSYM(neg5)
sub 0,x2,x2 /* negate x2 */
- addi 1,x2,x2 /* this can not overflow */
+ addi 1,x2,x2 /* this cannot overflow */
shd 0,x2,31,x1 /* get top bit (can be 1) */
sh1add x2,x2,x2 /* multiply by 3 to get started */
b LREF(neg)
GSYM($$divU_6)
.export $$divU_6,millicode
extru x2,30,31,x2 /* divide by 2 */
- addi 1,x2,x2 /* can not carry */
+ addi 1,x2,x2 /* cannot carry */
shd 0,x2,30,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(pos)
comb,< x2,0,LREF(neg10)
copy 0,x1
extru x2,30,31,x2 /* divide by 2 */
- addib,TR 1,x2,LREF(pos) /* add 1 (can not overflow) */
+ addib,TR 1,x2,LREF(pos) /* add 1 (cannot overflow) */
sh1add x2,x2,x2 /* multiply by 3 to get started */
LSYM(neg10)
GSYM($$divU_12)
.export $$divU_12,millicode
extru x2,29,30,x2 /* divide by 4 */
- addi 5,x2,t1 /* can not carry */
+ addi 5,x2,t1 /* cannot carry */
sh2add x2,t1,x2 /* multiply by 5 to get started */
b LREF(pos)
addc 0,0,x1
GSYM($$divI_17)
.export $$divI_17,millicode
comb,<,n x2,0,LREF(neg17)
- addi 1,x2,x2 /* this can not overflow */
+ addi 1,x2,x2 /* this cannot overflow */
shd 0,x2,28,t1 /* multiply by 0xf to get started */
shd x2,0,28,t2
sub t2,x2,x2
subb t1,0,x1
LSYM(neg17)
- subi 1,x2,x2 /* this can not overflow */
+ subi 1,x2,x2 /* this cannot overflow */
shd 0,x2,28,t1 /* multiply by 0xf to get started */
shd x2,0,28,t2
sub t2,x2,x2
.export $$divI_7,millicode
comb,<,n x2,0,LREF(neg7)
LSYM(7)
- addi 1,x2,x2 /* can not overflow */
+ addi 1,x2,x2 /* cannot overflow */
shd 0,x2,29,x1
sh3add x2,x2,x2
addc x1,0,x1
GSYM($$divI_9)
.export $$divI_9,millicode
comb,<,n x2,0,LREF(neg9)
- addi 1,x2,x2 /* can not overflow */
+ addi 1,x2,x2 /* cannot overflow */
shd 0,x2,29,t1
shd x2,0,29,t2
sub t2,x2,x2
This is for CSE to find several similar references, and only use one Z.
- X can either be a SYMBOL_REF or REG, but because combine can not
+ X can either be a SYMBOL_REF or REG, but because combine cannot
perform a 4->2 combination we do nothing for SYMBOL_REF + D where
D will not fit in 14 bits.
&& ! rtx_equal_p (operands[3], operands[5]))
return 0;
- /* Inout operand of add can not conflict with any operands from multiply. */
+ /* Inout operand of add cannot conflict with any operands from multiply. */
if (rtx_equal_p (operands[3], operands[0])
|| rtx_equal_p (operands[3], operands[1])
|| rtx_equal_p (operands[3], operands[2]))
return 0;
- /* multiply can not feed into addition operands. */
+ /* multiply cannot feed into addition operands. */
if (rtx_equal_p (operands[4], operands[0])
|| rtx_equal_p (operands[5], operands[0]))
return 0;
if (! rtx_equal_p (operands[3], operands[4]))
return 0;
- /* multiply can not feed into subtraction. */
+ /* multiply cannot feed into subtraction. */
if (rtx_equal_p (operands[5], operands[0]))
return 0;
- /* Inout operand of sub can not conflict with any operands from multiply. */
+ /* Inout operand of sub cannot conflict with any operands from multiply. */
if (rtx_equal_p (operands[3], operands[0])
|| rtx_equal_p (operands[3], operands[1])
|| rtx_equal_p (operands[3], operands[2]))
delay slot of the millicode call -- thus they act more like traditional
CALL_INSNs.
- Note we can not consider side effects of the insn to be delayed because
+ Note we cannot consider side effects of the insn to be delayed because
the branch and link insn will clobber the return pointer. If we happened
to use the return pointer in the delay slot of the call, then we lose.
delay slot of the millicode call -- thus they act more like traditional
CALL_INSNs.
- Note we can not consider side effects of the insn to be delayed because
+ Note we cannot consider side effects of the insn to be delayed because
the branch and link insn will clobber the return pointer. If we happened
to use the return pointer in the delay slot of the call, then we lose.
(define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
;; We don't simulate general issue queue (GIC). If we have SU insn
-;; and then SU1 insn, they can not be issued on the same cycle
+;; and then SU1 insn, they cannot be issued on the same cycle
;; (although SU1 insn and then SU insn can be issued) because the SU
;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
;; multipass insn scheduling will find the situation and issue the SU1
;; We could describe completion buffers slots in combination with the
;; retirement units and the order of completion but the result
-;; automaton would behave in the same way because we can not describe
+;; automaton would behave in the same way because we cannot describe
;; real latency time with taking in order completion into account.
;; Actually we could define the real latency time by querying reserved
;; automaton units but the current scheduler uses latency time before
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