case BI_FMA: return "fma";
case BI_FREXP: return "frexp";
case BI_LOAD: return "load";
+ case BI_LOAD_UNIFORM: return "load_uniform";
case BI_LOAD_ATTR: return "load_attr";
case BI_LOAD_VAR: return "load_var";
case BI_LOAD_VAR_ADDRESS: return "load_var_address";
if (ins->type == BI_MINMAX)
fprintf(fp, "%s", bi_minmax_mode_name(ins->minmax));
- else if (ins->type == BI_LOAD_ATTR || ins->type == BI_LOAD_VAR_ADDRESS)
+ else if (ins->type == BI_LOAD_ATTR || ins->type == BI_LOAD_VAR_ADDRESS || ins->type == BI_LOAD_UNIFORM)
bi_print_load(&ins->load, fp);
else if (ins->type == BI_LOAD_VAR)
bi_print_load_vary(&ins->load_vary, fp);
[BI_FMA] = BI_ROUNDMODE | BI_SCHED_FMA,
[BI_FREXP] = BI_SCHED_ALL,
[BI_LOAD] = BI_SCHED_HI_LATENCY,
+ [BI_LOAD_UNIFORM] = BI_SCHED_HI_LATENCY,
[BI_LOAD_ATTR] = BI_SCHED_HI_LATENCY,
[BI_LOAD_VAR] = BI_SCHED_HI_LATENCY,
[BI_LOAD_VAR_ADDRESS] = BI_SCHED_HI_LATENCY,
bi_emit(ctx, st);
}
+static void
+bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
+{
+ /* TODO: Indirect access */
+
+ bi_instruction ld = {
+ .type = BI_LOAD_UNIFORM,
+ .load = bi_direct_load_for_instr(instr),
+ .dest = bir_dest_index(&instr->dest),
+ .dest_type = nir_intrinsic_type(instr),
+ .src = {
+ BIR_INDEX_ZERO /* TODO: UBOs */
+ }
+ };
+
+ bi_emit(ctx, ld);
+}
+
static void
emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
{
else
unreachable("Unsupported shader stage");
break;
+
+ case nir_intrinsic_load_uniform:
+ bi_emit_ld_uniform(ctx, instr);
+ break;
+
default:
/* todo */
break;
BI_FMA,
BI_FREXP,
BI_LOAD,
+ BI_LOAD_UNIFORM,
BI_LOAD_ATTR,
BI_LOAD_VAR,
BI_LOAD_VAR_ADDRESS,
/* It can't get any worse than csel4... can it? */
#define BIR_SRC_COUNT 4
-/* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
+/* Class-specific data for BI_LOAD, BI_LD_ATTR, BI_LD_VAR_ADDR */
struct bi_load {
- /* Note: no indirects here */
+ /* Note: LD_ATTR does not support indirects */
unsigned location;
- /* Only for BI_LD_ATTR. But number of vector channels */
+ /* Number of vector channels */
unsigned channels;
};