fhdl: do not attempt slicing non-array signals to keep Verilog happy

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index f169b508f4c628b40001f70473243ffdde099b7a..4af82bd5949a500e509f1fefe1e3391e187c92e0 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -34,6 +34,12 @@ def _printexpr(ns, node):
                        raise TypeError
                return "(" + r + ")"
        elif isinstance(node, _Slice):
+               # Verilog does not like us slicing non-array signals...
+               if isinstance(node.value, Signal) \
+                 and node.value.bv.width == 1 \
+                 and node.start == 0 and node.stop == 1:
+                         return _printexpr(ns, node.value)
+
                if node.start + 1 == node.stop:
                        sr = "[" + str(node.start) + "]"
                else: