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diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
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--- a/openpower/sv/vector_ops.mdwn
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@@ -2,7 +2,8 @@
 
 # SV Vector Operations.
 
-TODO merge old standards page [[simple_v_extension/vector_ops/]]
+* TODO merge old standards page [[simple_v_extension/vector_ops/]]
+* bugreport <https://bugs.libre-soc.org/show_bug.cgi?id=142>
 
 The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)